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In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is *O*(*m*^{2}) in the worst-case, where *m* is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2746-2754

- Publication Date
- 2001/11/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Timing Analysis

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Shuji TSUKIYAMA, Masakazu TANAKA, Masahiro FUKUI, "An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2746-2754, November 2001, doi: .

Abstract: In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is *O*(*m*^{2}) in the worst-case, where *m* is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2746/_p

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@ARTICLE{e84-a_11_2746,

author={Shuji TSUKIYAMA, Masakazu TANAKA, Masahiro FUKUI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays},

year={2001},

volume={E84-A},

number={11},

pages={2746-2754},

abstract={In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is *O*(*m*^{2}) in the worst-case, where *m* is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.},

keywords={},

doi={},

ISSN={},

month={November},}

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TY - JOUR

TI - An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2746

EP - 2754

AU - Shuji TSUKIYAMA

AU - Masakazu TANAKA

AU - Masahiro FUKUI

PY - 2001

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E84-A

IS - 11

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - November 2001

AB - In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is *O*(*m*^{2}) in the worst-case, where *m* is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

ER -