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A novel *Multi-Level Partitioning* (MLP) technique taking into account *real-world constraints* for hardware-software partitioning in *Distributed Embedded Multiprocessor Systems* (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested *levels*. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed *Distributed Embedded System Codesign* (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.2 pp.614-626

- Publication Date
- 2001/02/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

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Trong-Yen LEE, Pao-Ann HSIUNG, Sao-Jie CHEN, "Hardware-Software Multi-Level Partitioning for Distributed Embedded Multiprocessor Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 2, pp. 614-626, February 2001, doi: .

Abstract: A novel *Multi-Level Partitioning* (MLP) technique taking into account *real-world constraints* for hardware-software partitioning in *Distributed Embedded Multiprocessor Systems* (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested *levels*. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed *Distributed Embedded System Codesign* (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_2_614/_p

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@ARTICLE{e84-a_2_614,

author={Trong-Yen LEE, Pao-Ann HSIUNG, Sao-Jie CHEN, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Hardware-Software Multi-Level Partitioning for Distributed Embedded Multiprocessor Systems},

year={2001},

volume={E84-A},

number={2},

pages={614-626},

abstract={A novel *Multi-Level Partitioning* (MLP) technique taking into account *real-world constraints* for hardware-software partitioning in *Distributed Embedded Multiprocessor Systems* (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested *levels*. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed *Distributed Embedded System Codesign* (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.},

keywords={},

doi={},

ISSN={},

month={February},}

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TY - JOUR

TI - Hardware-Software Multi-Level Partitioning for Distributed Embedded Multiprocessor Systems

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 614

EP - 626

AU - Trong-Yen LEE

AU - Pao-Ann HSIUNG

AU - Sao-Jie CHEN

PY - 2001

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E84-A

IS - 2

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - February 2001

AB - A novel *Multi-Level Partitioning* (MLP) technique taking into account *real-world constraints* for hardware-software partitioning in *Distributed Embedded Multiprocessor Systems* (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested *levels*. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed *Distributed Embedded System Codesign* (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.

ER -