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This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.9 pp.2255-2260

- Publication Date
- 2001/09/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- Digital Signal Processing

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Ichiro KURODA, Kouhei NADEHARA, "A Multimedia Architecture Extension for an Embedded RISC Processor" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 9, pp. 2255-2260, September 2001, doi: .

Abstract: This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_9_2255/_p

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@ARTICLE{e84-a_9_2255,

author={Ichiro KURODA, Kouhei NADEHARA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A Multimedia Architecture Extension for an Embedded RISC Processor},

year={2001},

volume={E84-A},

number={9},

pages={2255-2260},

abstract={This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.},

keywords={},

doi={},

ISSN={},

month={September},}

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TY - JOUR

TI - A Multimedia Architecture Extension for an Embedded RISC Processor

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2255

EP - 2260

AU - Ichiro KURODA

AU - Kouhei NADEHARA

PY - 2001

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E84-A

IS - 9

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - September 2001

AB - This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

ER -