In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.
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Gian Marco BO, Daniele D. CAVIGLIA, Maurizio VALLE, "A Self-Learning Analog Neural Processor" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 9, pp. 2149-2158, September 2002, doi: .
Abstract: In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_9_2149/_p
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@ARTICLE{e85-a_9_2149,
author={Gian Marco BO, Daniele D. CAVIGLIA, Maurizio VALLE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Self-Learning Analog Neural Processor},
year={2002},
volume={E85-A},
number={9},
pages={2149-2158},
abstract={In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - A Self-Learning Analog Neural Processor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2149
EP - 2158
AU - Gian Marco BO
AU - Daniele D. CAVIGLIA
AU - Maurizio VALLE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2002
AB - In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.
ER -