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Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors

Lu SUN, Bin WU, Tianchun YE

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Summary :

In this letter, a low latency, high throughput and hardware efficient sorted MMSE QR decomposition (MMSE-SQRD) for multiple-input multiple-output (MIMO) systems is presented. In contrast to the method of extending the complex matrix to real model and thereafter applying real-valued QR decomposition (QRD), we develop a highly parallel decomposition scheme based on coordinate rotation digital computer (CORDIC) which performs the QRD in complex domain directly and then converting the complex result to its real counterpart. The proposed scheme can greatly improve the processing parallelism and curtail the nullification and sorting procedures. Besides, we also design the corresponding pipelined hardware architecture of the MMSE-SQRD based on highly parallel Givens rotation structure with CORDIC algorithm for 4×4 MIMO detectors. The proposed MMSE-SQRD is implemented in SMIC 55nm CMOS technology achieving up to 50M QRD/s throughput and a latency of 59 clock cycles with only 218 kilo-gates (KG). Compared to the previous works, the proposed design achieves the highest normalized throughput efficiency and lowest processing latency.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E104-A No.4 pp.762-767
Publication Date
2021/04/01
Publicized
2020/10/12
Online ISSN
1745-1337
DOI
10.1587/transfun.2020EAL2076
Type of Manuscript
LETTER
Category
VLSI Design Technology and CAD

Authors

Lu SUN
  Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS),University of Chinese Academy of Sciences (UCAS)
Bin WU
  Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)
Tianchun YE
  Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)

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