Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.
Phuong T.K. DINH
the Hanoi University of Industry,the Hanoi University of Science and Technology
Linh T.T. DINH
the Hanoi University of Science and Technology
Tung T. TRAN
the Hanoi University of Science and Technology
Lam S. PHAM
the Hanoi University of Science and Technology
Han Le DUC
the Hanoi University of Science and Technology
Chi P. HOANG
the Hanoi University of Science and Technology
Minh D. NGUYEN
the Hanoi University of Science and Technology
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Phuong T.K. DINH, Linh T.T. DINH, Tung T. TRAN, Lam S. PHAM, Han Le DUC, Chi P. HOANG, Minh D. NGUYEN, "A Novel Fixed-Point Conversion Methodology For Digital Signal Processing Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 12, pp. 1537-1550, December 2022, doi: 10.1587/transfun.2021EAP1151.
Abstract: Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021EAP1151/_p
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@ARTICLE{e105-a_12_1537,
author={Phuong T.K. DINH, Linh T.T. DINH, Tung T. TRAN, Lam S. PHAM, Han Le DUC, Chi P. HOANG, Minh D. NGUYEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Novel Fixed-Point Conversion Methodology For Digital Signal Processing Systems},
year={2022},
volume={E105-A},
number={12},
pages={1537-1550},
abstract={Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.},
keywords={},
doi={10.1587/transfun.2021EAP1151},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - A Novel Fixed-Point Conversion Methodology For Digital Signal Processing Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1537
EP - 1550
AU - Phuong T.K. DINH
AU - Linh T.T. DINH
AU - Tung T. TRAN
AU - Lam S. PHAM
AU - Han Le DUC
AU - Chi P. HOANG
AU - Minh D. NGUYEN
PY - 2022
DO - 10.1587/transfun.2021EAP1151
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2022
AB - Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.
ER -