1. Introduction
Digital delta-sigma modulators (DDSMs) have become ubiquitous in modern wireless communication systems for their application in fractional-N phase locked loops (PLLs) [1]. In fractional-N PLLs, the modulator generates a digital output sequence that can be used to control a multi-modulus divider (MMD), as shown in Fig. 1, resulting in a fractional-N frequency that can be tuned with fine resolution less than the reference frequency. The modulator contains an \(n\)-bit digital input \(X\), and the modulator output sequence has the same average value as the input over the long haul, driving the MMD to work as a fractional-N divider.
Over the past few decades, researchers have developed various DSM structures to improve their spur and noise performances. One such structure is the MASH (multi-stage noise shaping) DDSM [2], which only requires adders and registers and has been widely used in commercial fractional-N PLL products. In MASH DDSMs, the quantization noise of interest is generated by the accumulator in the last stage and is shaped across multiple stages. As the order of the MASH DSM increases, the order of noise shaping also increases, which means more low-frequency noise power is pushed towards high frequencies. Assisted with a low-pass loop filter, this would greatly improve the in-band phase noise, along with integrated RMS jitter of fractional-N PLLs. However, due to the limited cycle length of the output sequence in DDSMs, there are still unwanted spurs in its output spectrum, which can limit the jitter and spur performances of a PLL and degrade the purity of the synthesized clock signal. Therefore, it is highly demanded to eliminate the spurious tones in DDSMs.
Previous works have proposed various solutions to mitigate unwanted spurs of DDSMs by randomizing the output sequence [3]-[5]. One popular way is to add dithering by introducing the pseudorandom binary sequence (PRBS) into the modulator with a linear feedback shift register (LFSR). The more randomized sequence means the quantization noise can be spread over a wider frequency range, thereby reducing spurs. However, conventional LFSR dithering requires extra hardware, penalizing the PLL’s area efficiency. A self-dithering technique was proposed in [7] to remove the LFSR, but the dithering can not work well in MASH DSM with shorter bit width. In this paper, a new MASH DSM structure is proposed to extend self-dithering method to DDSMs with shorter bit width.
2. Self-Dithered DDSM and Its Drawback
2.1 Introduction to Self-Dithered MASH DDSM
In [7], the authors utilized the quantization noise generated by the DSM itself to introduce dither instead of using an external LFSR. Specifically, for a MASH architecture, the quantization noise is derived from the most significant bit (MSB) of the last stage accumulator’s sum, as depicted in Fig. 2. The dithering signal \(D_n\) can be added either to the 1st stage of the MASH DSM or to the 2nd stage. The \(z\)-domain outputs for the two cases are respectively given by:
\[\begin{align} & Y_{\textit{MASH},\ \text{unshaped}}(z)=X(z)+D_n(z)+\left(1-{z^{-1}}\right)^3E(z) \tag{1} \\ &\hskip-3mm Y_{\textit{MASH},\ \text{shaped}}(z)=X(z)+\left(1-z^{-1}\right)D_n(z)+ \left(1-z^{-1}\right)^3E(z) \tag{2} \end{align}\] |
where \(E(z)\) is the quantization noise. When \(D_n\) is fed back to the 1st stage, the dithering signal appears at the output as it is, while it appears with 1st-order noise shaping when \(D_n\) is fed back to the 2nd stage. Thus, the former one is called an unshaped dithering while the latter one is called a shaped dithering.
Figure 3 demonstrates the effectiveness of the self-dithered MASH 1-1-1 for input bit widths of 16 at \(X = 1024\), where \(X\) indicates the input value for the DSM. The sample sequence is \(2^{16}\) for all the power spectral density (PSD) simulations. In particular, the suppression of spurs in this configuration occurs in a similar manner as LFSR-dithered MASH DDSMs in [6] with a 16-bit LFSR.
2.2 Drawback of Self-Dithered MASH DDSM
While the shaped self-dithered MASH DDSM can suppress the spurs just like LFSR-based MASH 1-1-1 and is generally preferred for its ability to effectively reduce low-frequency noise, it has been observed that spurious tones can still appear in the output spectra at low-bit inputs. As the input bit width decreases, these spurious tones become more pronounced, resulting in an increased noise floor. Specifically, for an \(n\)-bit DDSM with an input range of 0 to \(M-1\) (where \(M=2^n\)), the situation is worst when \(X=M/2\). Figure 4 illustrates the PSDs of the self-dithered MASH 1-1-1 with different bit widths at \(X=M/2\), which indicates that spurs are particularly noticeable in the output spectra of the shaped self-dithering when the input bit width is below 10 bits, and the situation is worse at 6 bits.
The issue of spurs in the output PSD can also be observed through the DSM’s minimum cycle length. A longer cycle length represents a more random output, which results in less noticeable spurs in the output PSD. Conversely, a shorter cycle length indicates a more periodic digital output, causing spurs to appear in the output PSD. In Fig. 5, the minimum cycle length is shown for the shaped dithering when \(n = 6\). It is evident that the shortest cycle length occurs at \(X = 32\) (\(M/2\)). Furthermore, even for inputs other than \(M/2\), like 21, 43, etc., the minimum cycle length is still not sufficiently long to prevent spurs from appearing in the output PSD.
The issue discussed above highlights the need to address spurs that occur in the self-dithered MASH 1-1-1 especially for low input bit widths. To mitigate these fractional spurs in the output spectra, we propose a self-dithered MASH 1-1-1-1 with shaped dithering, which will be detailed in the next section.
3. Improvement on Self-Dithered DDSM
For the self-dithered MASH 1-1-1 with shaped dithering, the 1-bit dither signal used in the self-dithered DSM is derived directly from the 3rd stage of the MASH 1-1-1 and can impact itself. If the dither signal is too autocorrelated, it will no longer be a white noise, and spurs will appear in the PSD. The impact of the 1-bit signal on itself increases as the input bit width decreases, leading to more noticeable spurs. Therefore, the primary objective of improving self-dithered DDSM is to reduce the autocorrelation of the dithering signal.
An approach to address the issue of spurs in the output spectra is to increase the order of the DSM, which can help to separate the source of dithering from where it is added. To achieve this, we propose a self-dithered MASH 1-1-1-1 as shown in Fig. 6, which can effectively mitigate the spurs that occur in the shaped dithering technique. Comparing to the previous self-dithered MASH 1-1-1, the proposed structure uses self-dithered technique with 4-stage MASH structure. The transfer function of the proposed structure is given by:
\[\begin{equation*} \hskip-1mm Y_{\textit{MASH},\ \text{shaped}}(z)=X(z)+\left(1-z^{-1}\right)D_n(z) +\left(1-z^{-1}\right)^4E(z). \tag{3} \end{equation*}\] |
In this approach, the dithering signal is generated from the MSB of the 4th stage accumulator’s sum and added to the 2nd stage to form a shaped dithering signal. The output PSDs of the self-dithered MASH 1-1-1-1 with shaped dithering are presented in Fig. 7(a). It can be observed from the figure that the PSD of the proposed method is similar to the PSD of the LFSR-based MASH 1-1-1-1 with a 16-bit LFSR, containing no noticeable spurs even when \(X=M/2\) at 6-bit input. Figure 7(b) compares the results when adding a dithering signal to the 1st, 2nd and 3rd stages, from which we can see that when adding a dithering signal to the 1st stage, the dithering signal is not shaped and results in a higher noise at low frequencies. When adding a dithering signal to the 3rd stage, the dithering signal still has a high autocorrelation and causes spurs in the output PSD.
Fig. 7 Output PSDs at 6-bit input with \(X=32\) (a) when comparing to previous methods and (b) dithering at different stages. |
The autocorrelations at \(X=32\) of the self-dithered MASH 1-1-1 and self-dithered MASH 1-1-1-1 are compared in Fig. 8 with a 6-bit input. For the self-dithered MASH 1-1-1 with shaped dithering, the spike beside the central spike appears at 70, indicating that the cycle length is 70 in this condition. On the other hand, for the proposed self-dithered MASH 1-1-1-1, high correlation coefficient appears only at the center, indicating the minimum sequence length is longer than 65536 at \(X=32\).
Fig. 8 Autocorrelations of (a) the self-dithered MASH 1-1-1 with shaped dithering and (b) the proposed self-dithered MASH 1-1-1-1 when \(X=32\) with a 6-bit input. |
By scanning all the inputs for 6-bits, as shown in Fig. 9, it is proven that the shortest cycle length is 63064 for the proposed method at \(X=56\), which is long enough to suppress the fractional spurs. Besides, for other inputs, the minimum cycle length is longer than 65536, which is the maximum sequence length within the simulation time.
Another benefit of using the self-dithered MASH 1-1-1-1 is its ability to provide additional quantization noise shaping as shown in Fig. 10 with a 6-bit input, resulting in a further reduction of in-band noise by pushing more noise power towards high frequencies. Despite its utilization of a 4-stage DSM, which is more complex compared to MASH 1-1-1, it does not require an additional LFSR to randomize the output sequence to suppress the spurs. Hence, the self-dithered MASH 1-1-1-1 not only addresses the issue of spurs in low-bit self-dithered MASH 1-1-1 without LFSR, but also achieves 4th order noise shaping.
According to [8], the impact of the DSM’s quantization noise on the phase noise of the fractional-N PLL is given by
\[\begin{equation*} \Gamma_{\Delta\Sigma,\mathit{div}}=S_{qn}\cdot\frac{(2\pi)^2}{\left|1-z^{-1}\right|^2} \cdot \frac{1}{N^2}\cdot\left|N\cdot\frac{G(s)}{1+G(s)}\right|^2. \tag{4} \end{equation*}\] |
In this equation, \(G(s)\) represents the open-loop transfer function of the PLL, \(S_{qn}\) denotes the output power spectral density (PSD) of the DSM, and \(N\) is the division ratio. For example, Fig. 11 shows the PLL phase noise when the loop bandwidth is configured to 289 kHz with a 3rd order filter and 20 MHz DSM clock frequency. The integer portion of the division ratio is set to 32. All DSMs operate with a 6-bit input and a fractional part of 0.5 (\(X=32\)), which is the worst case for spur generation. The phase noise was obtained from a \(2^{16}\) sample sequence. The undithered DSM in the fractional-N PLL produces obvious spurs with the maximum level of \(-63.39\) dBc/Hz. The shaped self-dithered MASH 1-1-1 generates fractional spurs with the maximum level of \(-74.42\) dBc/Hz. In contrast, the proposed self-dithered MASH 1-1-1-1 with shaped dithering effectively suppresses the fractional spurs, resulting in a phase noise contribution of around \(-90\) dBc/Hz, similar to the LFSR-dithered DSM. Consequently, the proposed method exhibits no spurs even at low input bits without using an external LFSR.
Fig. 11 Phase noise of a fractional-N PLL with (a) the LFSR-dithered MASH 1-1-1 and (b) the proposed self-dithered MASH 1-1-1-1. |
In Fig. 11, thanks to the 4th-order noise shaping of the MASH 1-1-1-1 structure, the phase noise of the proposed method is reduced especially around the 1 MHz offset frequency when compared to that of the LFSR-based MASH 1-1-1 configuration. In addition, the phase noise pushed to the higher offset frequencies by the higher-order noise shaping is well suppressed by the PLL loop characteristic. The integrated jitter due to the DSM quantization noise within the frequency range of 100 kHz to 10 MHz with the proposed self-dithered MASH 1-1-1-1 is 24.3 ps_{rms}, while employing the LFSR-based MASH 1-1-1 results in 29.3 ps_{rms}. This result demonstrates that with the 4th-order noise shaping, a lower phase noise and jitter can be achieved in the fractional-N PLL with a proper bandwidth.
Table 1 shows the comparison of the predicted circuit scale between the proposed self-dithered MASH 1-1-1-1 and the traditional LFSR-based MASH 1-1-1 structures with logic-synthesized results before place-and-route, using TSMC 65nm CMOS technology with a 100 MHz clock and a 6-bit input as an example case. The LFSR is implemented with a 16-bit configuration as was used in the discussions in the previous sections, which is sufficient for generating a suitably random dithering signal. The gate count in the table is the total cell area normalized by the area of the minimum NAND2 cell. Compared with the LFSR-based MASH 1-1-1, the proposed technique requires slightly larger cell area for one more accumulator even without a dedicated LFSR, while it requires less DFFs, which could relax the overhead of clock tree synthesis during the subsequent place-and-route. In total, compared with the prior LFSR-based method, we can expect similar total area occupation with slightly less power consumption using the proposed method that achieves an extra order of noise shaping.
4. Conclusions
DDSMs are essential components in fractional-N PLLs, which need to suppress fractional spurs in its output PSD and reduce in-band noise. This paper focuses on the investigation of the issue and the limitation in self-dithered MASH DDSMs. To address the issue of spurs at low input bit width in the previous self-dithered MASH 1-1-1 DDSM with shaped dithering, we proposed to use the self-dithering in MASH 1-1-1-1. The proposed self-dithered MASH 1-1-1-1 suppresses the fractional spurs even at low input bits with no external LFSR and achieves an extra order of noise shaping.
Acknowledgments
This work was supported in part by the Institute for AI and Beyond, The University of Tokyo, and in part by the Japan Society for the Promotion of Science (JSPS) KAKENHI un-der Grant JP21H03406 and Grant JP21J21917.
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