Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.
Yuya USHIODA
Japan Advanced Institute of Science and Technology (JAIST)
Mineo KANEKO
Japan Advanced Institute of Science and Technology (JAIST)
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Yuya USHIODA, Mineo KANEKO, "ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 3, pp. 600-609, March 2024, doi: 10.1587/transfun.2023VLP0020.
Abstract: Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0020/_p
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@ARTICLE{e107-a_3_600,
author={Yuya USHIODA, Mineo KANEKO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits},
year={2024},
volume={E107-A},
number={3},
pages={600-609},
abstract={Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.},
keywords={},
doi={10.1587/transfun.2023VLP0020},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 600
EP - 609
AU - Yuya USHIODA
AU - Mineo KANEKO
PY - 2024
DO - 10.1587/transfun.2023VLP0020
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.
ER -