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ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits

Yuya USHIODA, Mineo KANEKO

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Summary :

Adiabatic logic circuits are regarded as one of the most attractive solutions for low-power circuit design. This study is dedicated to optimizing the design of the Two-Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi-adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined 2LAL, and we propose two ILP approaches for minimizing hardware cost through optimization of early decompute. In the first approach, the problem is formulated as a kind of scheduling problem, while it is reformulated as node selection problem (stable set problem). The performance of the proposed methods are evaluated using several benchmark circuits from ISCAS-85, and the maximum 70% hardware reduction is observed compared with an existing method.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.3 pp.600-609
Publication Date
2024/03/01
Publicized
2023/09/04
Online ISSN
1745-1337
DOI
10.1587/transfun.2023VLP0020
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
VLSI Design Technology and CAD

Authors

Yuya USHIODA
  Japan Advanced Institute of Science and Technology (JAIST)
Mineo KANEKO
  Japan Advanced Institute of Science and Technology (JAIST)

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