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Non-volatile memories are a promising alternative to memory design but data stored in them still may be destructed due to crosstalk and radiation. The data stored in them can be restored by using error-correcting codes but they require extra bits to correct bit errors. One of the largest problems in non-volatile memories is that they consume ten to hundred times more energy than normal memories in bit-writing. It is quite necessary to reduce writing bits. Recently, a REC code (bit-write-reducing and error-correcting code) is proposed for non-volatile memories which can reduce writing bits and has a capability of error correction. The REC code is generated from a linear systematic error-correcting code but it must include the codeword of all 1's, i.e., 11…1. The codeword bit length must be longer in order to satisfy this condition. In this letter, we propose a method to generate a relaxed REC code which is generated from a relaxed error-correcting code, which does not necessarily include the codeword of all 1's and thus its codeword bit length can be shorter. We prove that the *maximum flipping bits* of the relaxed REC code is still limited theoretically. Experimental results show that the relaxed REC code efficiently reduce the number of writing bits.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.7 pp.1045-1052

- Publication Date
- 2018/07/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E101.A.1045

- Type of Manuscript
- Special Section LETTER (Special Section on Design Methodologies for System on a Chip)

- Category

Tatsuro KOJO

Waseda University

Masashi TAWADA

Waseda University

Masao YANAGISAWA

Waseda University

Nozomu TOGAWA

Waseda University

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Tatsuro KOJO, Masashi TAWADA, Masao YANAGISAWA, Nozomu TOGAWA, "A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 7, pp. 1045-1052, July 2018, doi: 10.1587/transfun.E101.A.1045.

Abstract: Non-volatile memories are a promising alternative to memory design but data stored in them still may be destructed due to crosstalk and radiation. The data stored in them can be restored by using error-correcting codes but they require extra bits to correct bit errors. One of the largest problems in non-volatile memories is that they consume ten to hundred times more energy than normal memories in bit-writing. It is quite necessary to reduce writing bits. Recently, a REC code (bit-write-reducing and error-correcting code) is proposed for non-volatile memories which can reduce writing bits and has a capability of error correction. The REC code is generated from a linear systematic error-correcting code but it must include the codeword of all 1's, i.e., 11…1. The codeword bit length must be longer in order to satisfy this condition. In this letter, we propose a method to generate a relaxed REC code which is generated from a relaxed error-correcting code, which does not necessarily include the codeword of all 1's and thus its codeword bit length can be shorter. We prove that the *maximum flipping bits* of the relaxed REC code is still limited theoretically. Experimental results show that the relaxed REC code efficiently reduce the number of writing bits.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.1045/_p

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@ARTICLE{e101-a_7_1045,

author={Tatsuro KOJO, Masashi TAWADA, Masao YANAGISAWA, Nozomu TOGAWA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories},

year={2018},

volume={E101-A},

number={7},

pages={1045-1052},

abstract={Non-volatile memories are a promising alternative to memory design but data stored in them still may be destructed due to crosstalk and radiation. The data stored in them can be restored by using error-correcting codes but they require extra bits to correct bit errors. One of the largest problems in non-volatile memories is that they consume ten to hundred times more energy than normal memories in bit-writing. It is quite necessary to reduce writing bits. Recently, a REC code (bit-write-reducing and error-correcting code) is proposed for non-volatile memories which can reduce writing bits and has a capability of error correction. The REC code is generated from a linear systematic error-correcting code but it must include the codeword of all 1's, i.e., 11…1. The codeword bit length must be longer in order to satisfy this condition. In this letter, we propose a method to generate a relaxed REC code which is generated from a relaxed error-correcting code, which does not necessarily include the codeword of all 1's and thus its codeword bit length can be shorter. We prove that the *maximum flipping bits* of the relaxed REC code is still limited theoretically. Experimental results show that the relaxed REC code efficiently reduce the number of writing bits.},

keywords={},

doi={10.1587/transfun.E101.A.1045},

ISSN={1745-1337},

month={July},}

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TY - JOUR

TI - A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1045

EP - 1052

AU - Tatsuro KOJO

AU - Masashi TAWADA

AU - Masao YANAGISAWA

AU - Nozomu TOGAWA

PY - 2018

DO - 10.1587/transfun.E101.A.1045

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E101-A

IS - 7

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - July 2018

AB - Non-volatile memories are a promising alternative to memory design but data stored in them still may be destructed due to crosstalk and radiation. The data stored in them can be restored by using error-correcting codes but they require extra bits to correct bit errors. One of the largest problems in non-volatile memories is that they consume ten to hundred times more energy than normal memories in bit-writing. It is quite necessary to reduce writing bits. Recently, a REC code (bit-write-reducing and error-correcting code) is proposed for non-volatile memories which can reduce writing bits and has a capability of error correction. The REC code is generated from a linear systematic error-correcting code but it must include the codeword of all 1's, i.e., 11…1. The codeword bit length must be longer in order to satisfy this condition. In this letter, we propose a method to generate a relaxed REC code which is generated from a relaxed error-correcting code, which does not necessarily include the codeword of all 1's and thus its codeword bit length can be shorter. We prove that the *maximum flipping bits* of the relaxed REC code is still limited theoretically. Experimental results show that the relaxed REC code efficiently reduce the number of writing bits.

ER -