The search functionality is under construction.
The search functionality is under construction.

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing

Hongjie XU, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA

  • Full Text Views

    0

  • Cite this

Summary :

This paper focuses on power-area trade-off axis to memory systems. Compared with the power-performance-area trade-off application on the traditional high performance cache, this paper focuses on the edge processing environment which is becoming more and more important in the Internet of Things (IoT) era. A new power-oriented trade-off is proposed for on-chip cache architecture. As a case study, this paper exploits a good energy efficiency of Standard-Cell Memory (SCM) operating in a near-threshold voltage region and a good area efficiency of Static Random Access Memory (SRAM). A hybrid 2-level on-chip cache structure is first introduced as a replacement of 6T-SRAM cache as L0 cache to save the energy consumption. This paper proposes a method for finding the best capacity combination for SCM and SRAM, which minimizes the energy consumption of the hybrid cache under a specific cache area constraint. The simulation result using a 65-nm process technology shows that up to 80% energy consumption is reduced without increasing the die area by replacing the conventional SRAM instruction cache with the hybrid 2-level cache. The result shows that energy consumption can be reduced if the area constraint for the proposed hybrid cache system is less than the area which is equivalent to a 8kB SRAM. If the target operating frequency is less than 100MHz, energy reduction can be achieved, which implies that the proposed cache system is suitable for low-power systems where a moderate processing speed is required.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.12 pp.1741-1750
Publication Date
2019/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E102.A.1741
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Hongjie XU
  Kyoto University
Jun SHIOMI
  Kyoto University
Tohru ISHIHARA
  Nagoya University
Hidetoshi ONODERA
  Kyoto University

Keyword