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This paper describes the application techniques of the latency insertion method (LIM) to CMOS circuit simulations. Though the existing LIM algorithm to CMOS circuit performs fast transient analysis, CMOS circuits are not modeled accurately. As a result, they do not provide accurate simulations. We propose a more accurate LIM scheme for the CMOS inverter circuit by adopting a more accurate model of the CMOS inverter characteristics. Moreover, we present the way to expand the LIM algorithm to general CMOS circuit simulations. In order to apply LIM to the general CMOS circuits which consist of CMOS NAND and NOR, we derive the updating formulas of the explicit form of the LIM algorithm. By using the explicit form of the LIM scheme, it becomes easy to take in the characteristics of CMOS NAND and NOR into the LIM simulations. As a result, it is confirmed that our techniques are useful and efficient for the simulations of CMOS circuits.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.10 pp.2546-2553

- Publication Date
- 2009/10/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E92.A.2546

- Type of Manuscript
- Special Section PAPER (Special Section on Nonlinear Theory and its Applications)

- Category
- Nonlinear Problems

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Tadatoshi SEKINE, Hideki ASAI, "CMOS Circuit Simulation Using Latency Insertion Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 10, pp. 2546-2553, October 2009, doi: 10.1587/transfun.E92.A.2546.

Abstract: This paper describes the application techniques of the latency insertion method (LIM) to CMOS circuit simulations. Though the existing LIM algorithm to CMOS circuit performs fast transient analysis, CMOS circuits are not modeled accurately. As a result, they do not provide accurate simulations. We propose a more accurate LIM scheme for the CMOS inverter circuit by adopting a more accurate model of the CMOS inverter characteristics. Moreover, we present the way to expand the LIM algorithm to general CMOS circuit simulations. In order to apply LIM to the general CMOS circuits which consist of CMOS NAND and NOR, we derive the updating formulas of the explicit form of the LIM algorithm. By using the explicit form of the LIM scheme, it becomes easy to take in the characteristics of CMOS NAND and NOR into the LIM simulations. As a result, it is confirmed that our techniques are useful and efficient for the simulations of CMOS circuits.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2546/_p

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@ARTICLE{e92-a_10_2546,

author={Tadatoshi SEKINE, Hideki ASAI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={CMOS Circuit Simulation Using Latency Insertion Method},

year={2009},

volume={E92-A},

number={10},

pages={2546-2553},

abstract={This paper describes the application techniques of the latency insertion method (LIM) to CMOS circuit simulations. Though the existing LIM algorithm to CMOS circuit performs fast transient analysis, CMOS circuits are not modeled accurately. As a result, they do not provide accurate simulations. We propose a more accurate LIM scheme for the CMOS inverter circuit by adopting a more accurate model of the CMOS inverter characteristics. Moreover, we present the way to expand the LIM algorithm to general CMOS circuit simulations. In order to apply LIM to the general CMOS circuits which consist of CMOS NAND and NOR, we derive the updating formulas of the explicit form of the LIM algorithm. By using the explicit form of the LIM scheme, it becomes easy to take in the characteristics of CMOS NAND and NOR into the LIM simulations. As a result, it is confirmed that our techniques are useful and efficient for the simulations of CMOS circuits.},

keywords={},

doi={10.1587/transfun.E92.A.2546},

ISSN={1745-1337},

month={October},}

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TY - JOUR

TI - CMOS Circuit Simulation Using Latency Insertion Method

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2546

EP - 2553

AU - Tadatoshi SEKINE

AU - Hideki ASAI

PY - 2009

DO - 10.1587/transfun.E92.A.2546

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E92-A

IS - 10

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - October 2009

AB - This paper describes the application techniques of the latency insertion method (LIM) to CMOS circuit simulations. Though the existing LIM algorithm to CMOS circuit performs fast transient analysis, CMOS circuits are not modeled accurately. As a result, they do not provide accurate simulations. We propose a more accurate LIM scheme for the CMOS inverter circuit by adopting a more accurate model of the CMOS inverter characteristics. Moreover, we present the way to expand the LIM algorithm to general CMOS circuit simulations. In order to apply LIM to the general CMOS circuits which consist of CMOS NAND and NOR, we derive the updating formulas of the explicit form of the LIM algorithm. By using the explicit form of the LIM scheme, it becomes easy to take in the characteristics of CMOS NAND and NOR into the LIM simulations. As a result, it is confirmed that our techniques are useful and efficient for the simulations of CMOS circuits.

ER -