In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.
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Jinhyun CHO, Doowon LEE, Sangyong YOON, Sanggyu PARK, Soo-Ik CHAE, "VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 1, pp. 279-290, January 2009, doi: 10.1587/transfun.E92.A.279.
Abstract: In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.279/_p
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@ARTICLE{e92-a_1_279,
author={Jinhyun CHO, Doowon LEE, Sangyong YOON, Sanggyu PARK, Soo-Ik CHAE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications},
year={2009},
volume={E92-A},
number={1},
pages={279-290},
abstract={In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.},
keywords={},
doi={10.1587/transfun.E92.A.279},
ISSN={1745-1337},
month={January},}
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TY - JOUR
TI - VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 279
EP - 290
AU - Jinhyun CHO
AU - Doowon LEE
AU - Sangyong YOON
AU - Sanggyu PARK
AU - Soo-Ik CHAE
PY - 2009
DO - 10.1587/transfun.E92.A.279
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2009
AB - In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.
ER -