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VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Jinhyun CHO, Doowon LEE, Sangyong YOON, Sanggyu PARK, Soo-Ik CHAE

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Summary :

In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.1 pp.279-290
Publication Date
2009/01/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E92.A.279
Type of Manuscript
PAPER
Category
VLSI Design Technology and CAD

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