In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
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Chia-I CHEN, Juinn-Dar HUANG, "A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1300-1308, July 2010, doi: 10.1587/transfun.E93.A.1300.
Abstract: In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1300/_p
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@ARTICLE{e93-a_7_1300,
author={Chia-I CHEN, Juinn-Dar HUANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication},
year={2010},
volume={E93-A},
number={7},
pages={1300-1308},
abstract={In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.},
keywords={},
doi={10.1587/transfun.E93.A.1300},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1300
EP - 1308
AU - Chia-I CHEN
AU - Juinn-Dar HUANG
PY - 2010
DO - 10.1587/transfun.E93.A.1300
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
ER -