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For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.11 pp.1949-1957

- Publication Date
- 2010/11/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E93.A.1949

- Type of Manuscript
- Special Section PAPER (Special Section on Information Theory and Its Applications)

- Category
- Coding Theory

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Kenta KASAI, Kohichi SAKANIWA, "Fourier Domain Decoding Algorithm of Non-binary LDPC Codes for Parallel Implementation" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 11, pp. 1949-1957, November 2010, doi: 10.1587/transfun.E93.A.1949.

Abstract: For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1949/_p

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@ARTICLE{e93-a_11_1949,

author={Kenta KASAI, Kohichi SAKANIWA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Fourier Domain Decoding Algorithm of Non-binary LDPC Codes for Parallel Implementation},

year={2010},

volume={E93-A},

number={11},

pages={1949-1957},

abstract={For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.},

keywords={},

doi={10.1587/transfun.E93.A.1949},

ISSN={1745-1337},

month={November},}

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TY - JOUR

TI - Fourier Domain Decoding Algorithm of Non-binary LDPC Codes for Parallel Implementation

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1949

EP - 1957

AU - Kenta KASAI

AU - Kohichi SAKANIWA

PY - 2010

DO - 10.1587/transfun.E93.A.1949

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E93-A

IS - 11

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - November 2010

AB - For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

ER -