In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.
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Chia-Yu LIN, Chih-Chun WEI, Mong-Kai KU, "Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 2, pp. 773-780, February 2011, doi: 10.1587/transfun.E94.A.773.
Abstract: In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.773/_p
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@ARTICLE{e94-a_2_773,
author={Chia-Yu LIN, Chih-Chun WEI, Mong-Kai KU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes},
year={2011},
volume={E94-A},
number={2},
pages={773-780},
abstract={In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.},
keywords={},
doi={10.1587/transfun.E94.A.773},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 773
EP - 780
AU - Chia-Yu LIN
AU - Chih-Chun WEI
AU - Mong-Kai KU
PY - 2011
DO - 10.1587/transfun.E94.A.773
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2011
AB - In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.
ER -