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Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes

Chia-Yu LIN, Chih-Chun WEI, Mong-Kai KU

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Summary :

In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.2 pp.773-780
Publication Date
2011/02/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E94.A.773
Type of Manuscript
PAPER
Category
Coding Theory

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