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Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description

Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, Rene CUMPLIDO, Miguel MORALES-SANDOVAL

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Summary :

MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

Publication
IEICE TRANSACTIONS on Information Vol.E91-D No.10 pp.2519-2523
Publication Date
2008/10/01
Publicized
Online ISSN
1745-1361
DOI
10.1093/ietisy/e91-d.10.2519
Type of Manuscript
LETTER
Category
VLSI Systems

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