A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
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Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, "A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 11, pp. 1466-1473, November 1999, doi: .
Abstract: A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_11_1466/_p
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@ARTICLE{e82-d_11_1466,
author={Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Information},
title={A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits},
year={1999},
volume={E82-D},
number={11},
pages={1466-1473},
abstract={A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1466
EP - 1473
AU - Hiroshi TAKAHASHI
AU - Kwame Osei BOATENG
AU - Yuzo TAKAMATSU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 1999
AB - A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
ER -