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A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a *p*-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus *m*, 2^{p}-1*m* ^{p}+2^{p-1}-1, in a residue number system (RNS), the modulo *m* addition is performed by using two *p*-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo *m* addition time is independent of the word length of operands. When *m*=2^{p} or *m*= 2^{p} *m* addition is implemented by using only one SD adder. Moreover, a modulo *m* multiplier is constructed using a binary modulo *m* SD adder tree, and the modulo *m* multiplication can be performed in a time proportional to log _{2} *p*. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

- Publication
- IEICE TRANSACTIONS on Information Vol.E83-D No.12 pp.2056-2064

- Publication Date
- 2000/12/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- Theory/Models of Computation

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Shugang WEI, Kensuke SHIMIZU, "A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation" in IEICE TRANSACTIONS on Information,
vol. E83-D, no. 12, pp. 2056-2064, December 2000, doi: .

Abstract: A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a *p*-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus *m*, 2^{p}-1*m* ^{p}+2^{p-1}-1, in a residue number system (RNS), the modulo *m* addition is performed by using two *p*-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo *m* addition time is independent of the word length of operands. When *m*=2^{p} or *m*= 2^{p} *m* addition is implemented by using only one SD adder. Moreover, a modulo *m* multiplier is constructed using a binary modulo *m* SD adder tree, and the modulo *m* multiplication can be performed in a time proportional to log _{2} *p*. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

URL: https://global.ieice.org/en_transactions/information/10.1587/e83-d_12_2056/_p

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@ARTICLE{e83-d_12_2056,

author={Shugang WEI, Kensuke SHIMIZU, },

journal={IEICE TRANSACTIONS on Information},

title={A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation},

year={2000},

volume={E83-D},

number={12},

pages={2056-2064},

abstract={A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a *p*-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus *m*, 2^{p}-1*m* ^{p}+2^{p-1}-1, in a residue number system (RNS), the modulo *m* addition is performed by using two *p*-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo *m* addition time is independent of the word length of operands. When *m*=2^{p} or *m*= 2^{p} *m* addition is implemented by using only one SD adder. Moreover, a modulo *m* multiplier is constructed using a binary modulo *m* SD adder tree, and the modulo *m* multiplication can be performed in a time proportional to log _{2} *p*. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

keywords={},

doi={},

ISSN={},

month={December},}

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TY - JOUR

TI - A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation

T2 - IEICE TRANSACTIONS on Information

SP - 2056

EP - 2064

AU - Shugang WEI

AU - Kensuke SHIMIZU

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Information

SN -

VL - E83-D

IS - 12

JA - IEICE TRANSACTIONS on Information

Y1 - December 2000

AB - A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a *p*-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus *m*, 2^{p}-1*m* ^{p}+2^{p-1}-1, in a residue number system (RNS), the modulo *m* addition is performed by using two *p*-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo *m* addition time is independent of the word length of operands. When *m*=2^{p} or *m*= 2^{p} *m* addition is implemented by using only one SD adder. Moreover, a modulo *m* multiplier is constructed using a binary modulo *m* SD adder tree, and the modulo *m* multiplication can be performed in a time proportional to log _{2} *p*. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

ER -