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Average Power Reduction in Scan Testing by Test Vector Modification

Seiji KAJIHARA, Koji ISHIDA, Kohei MIYASE

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Summary :

This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 45% of the original test sets in average.

Publication
IEICE TRANSACTIONS on Information Vol.E85-D No.10 pp.1483-1489
Publication Date
2002/10/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category
Test Generation and Modification

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