The search functionality is under construction.

The search functionality is under construction.

In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2073-2079

- Publication Date
- 2010/08/01

- Publicized

- Online ISSN
- 1745-1361

- DOI
- 10.1587/transinf.E93.D.2073

- Type of Manuscript
- Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)

- Category
- Multiple-Valued VLSI Technology

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

Copy

Motoi INABA, Koichi TANNO, Hiroki TAMURA, Okihiko ISHIZUKA, "Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2073-2079, August 2010, doi: 10.1587/transinf.E93.D.2073.

Abstract: In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2073/_p

Copy

@ARTICLE{e93-d_8_2073,

author={Motoi INABA, Koichi TANNO, Hiroki TAMURA, Okihiko ISHIZUKA, },

journal={IEICE TRANSACTIONS on Information},

title={Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits},

year={2010},

volume={E93-D},

number={8},

pages={2073-2079},

abstract={In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.},

keywords={},

doi={10.1587/transinf.E93.D.2073},

ISSN={1745-1361},

month={August},}

Copy

TY - JOUR

TI - Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits

T2 - IEICE TRANSACTIONS on Information

SP - 2073

EP - 2079

AU - Motoi INABA

AU - Koichi TANNO

AU - Hiroki TAMURA

AU - Okihiko ISHIZUKA

PY - 2010

DO - 10.1587/transinf.E93.D.2073

JO - IEICE TRANSACTIONS on Information

SN - 1745-1361

VL - E93-D

IS - 8

JA - IEICE TRANSACTIONS on Information

Y1 - August 2010

AB - In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

ER -