The search functionality is under construction.

The search functionality is under construction.

This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.

- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2162-2171

- Publication Date
- 2010/08/01

- Publicized

- Online ISSN
- 1745-1361

- DOI
- 10.1587/transinf.E93.D.2162

- Type of Manuscript
- PAPER

- Category
- Software System

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

Copy

Sung-Rae LEE, Ser-Hoon LEE, Sun-Young HWANG, "A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2162-2171, August 2010, doi: 10.1587/transinf.E93.D.2162.

Abstract: This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.

URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2162/_p

Copy

@ARTICLE{e93-d_8_2162,

author={Sung-Rae LEE, Ser-Hoon LEE, Sun-Young HWANG, },

journal={IEICE TRANSACTIONS on Information},

title={A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems},

year={2010},

volume={E93-D},

number={8},

pages={2162-2171},

abstract={This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.},

keywords={},

doi={10.1587/transinf.E93.D.2162},

ISSN={1745-1361},

month={August},}

Copy

TY - JOUR

TI - A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems

T2 - IEICE TRANSACTIONS on Information

SP - 2162

EP - 2171

AU - Sung-Rae LEE

AU - Ser-Hoon LEE

AU - Sun-Young HWANG

PY - 2010

DO - 10.1587/transinf.E93.D.2162

JO - IEICE TRANSACTIONS on Information

SN - 1745-1361

VL - E93-D

IS - 8

JA - IEICE TRANSACTIONS on Information

Y1 - August 2010

AB - This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.

ER -