Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

A wideband dual-line polarized antenna with low-profile property is presented in this paper. The dual-polarized antenna consists of two crossed antenna elements over a metal reflector and is excited by RF connectors vertically. Here, the crossed antenna element is based on Vivaldi radiator to obtain wideband performance. By loading resistors on the patches of Vivaldi radiator, not only the impedance matching of the proposed antenna can be improved further but also the profile is reduced greatly. Whatever, the loaded resistors can also depress radiation efficiency of the antenna element to a certain extent, especially in the lower band. For this reason, three periodic slots etched on the Vivaldi radiator are introduced herein to enhance the gain performance. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of a relative bandwidth of 153% for VSWR ≤ 2 (2-15 GHz) and a low profile of 0.22 λ_L (in terms of the lowest frequency of the band). Besides, the prototype can achieve an average gain of approximately 5 dBi and a maximum radiation efficiency of 80% within passband.

The novel rare earth variable flux permanent magnet synchronous motor (PMSM) for electric vehicles is proposed. The structure and magnetic field regulation characteristics are analyzed, the variation of magnetic density, no-load back electromagnetic force and output torque with speed was studied through finite element simulation. The weak magnetic field expansion speed performance of the novel PMSM has been verified through experimental equipment. The adjustable electromagnetic field with running speed on the rare earth PMSM increases the high-speed operation range of vehicle.

In order to solve the problems of the traditional model reference adaptive system (MRAS) speed estimation adaptive mechanism, such as poor tracking accuracy and slow response, A new dual sliding mode adaptive observer is designed to estimate the rotational speed and rotor position of permanent magnet synchronous motor (PMSM). Firstly, a new two-variable complex reaching law is used to replace the traditional first-order sliding mode for velocity loop control, and an anti-saturation scheme is introduced to improve the anti-interference ability of the system. Secondly, the PI adaptive mechanism in the traditional MRAS is replaced by a new super-twisting weighted integral type algorithm adaptive observer (STWITA-AO), which effectively speeds up the convergence of the estimated speed and reduces the inherent chattering of the sliding mode structure. Finally, the relevant simulation is compared and verified. The simulation results show that the estimation strategy based on the new double sliding mode MRAS control can make the speed estimate converge to the actual value faster, and improve the dynamic performance and robustness of the observer.

A wideband crossed dipole antenna for dual-polarized applications is presented in this paper. The antenna consists of a printed crossed dipole radiator loaded with periodic slots, four metal posts, four metal sidewalls and a metal reflector. The crossed dipole antenna is directly fed by a simple coaxial cable, achieving stable dual-polarization radiation characteristics. Here, two approaches are adopted to adjust the high and low resonant frequency of the antenna with large freedom. Firstly, four metal posts are introduced into conventional crossed dipole antenna, and their distance from the feeding point can independently adjust the lower resonant mode. Secondly, periodic slots are etched on the crossed dipole arms, and the upper resonant frequency can be controlled independently by altering the length of these slots. Also, the metal sidewalls on the ground are used herein to obtain enhanced gain property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The measured results show good performance of a relative bandwidth of 64.3% for VSWR ≤ 2 (1.32-2.57 GHz). Moreover, the antenna has good unidirectional radiation performance and can achieve maximum gain of 9.1 dBi at 2.3 GHz.

Wireless power transfer requires multilevel energy conversion for energy transfer, resulting in a bulky system. This paper proposes a direct AC-AC converter topology denoted as double half-bridge series-matrix converter and introduces a symmetric modulation method that eliminates the need for input voltage polarity detection. The converter circumvents DC conversion and operates at a unit power factor without the assistance of power factor correction. A 1kw prototype was constructed and the same control strategy was adopted, without considering the polarity or magnitude of the input voltage, verifying the accuracy and reliability of the proposed topology. The transmission efficiency was achieved at 91.43%.

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000∼100000 LUTs comparing with existing methods, with full fault coverage.

This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

This paper aims to establish a mathematical error model for surface temperature measurement based on FBG and to enhance its measurement precision. Firstly, an improved temperature-sensing model for FBG was established. Subsequently, the mathematical model for FBG-based surface temperature measurement error was developed. The experiments were conducted using a controllable surface heat source. Experimental results demonstrate good consistency among the errors obtained from the mathematical model, the finite element model, and experimental testing. Finally, corrosion processing and thermally conductive silicone packaging methods were proposed, elevating the bare FBG's surface temperature measurement accuracy from approximately 4°C to approximately 1°C.

This paper presents a 2: 1 analog multiplexer (AMUX) using IHP’s 130-nm SiGe BiCMOS process. The proposed AMUX expands the analog bandwidth (BW) of CMOS-based DACs by introducing interleaving sampling technique, thus improving the data rate of single lane in modern optical communication systems. Meanwhile, a detailed analysis of process selection which particularly focuses on material and device considerations is adopted, and a principle of the BW expansion is comprehensively discussed. The AMUX exhibits a BW >70 GHz, achieving a data rate of 200 Gb/s under PAM-4 modulation.

This article proposes a wide input voltage range DC-DC buck converter based on AOT control mode, which can be used in low-power applications such as the Internet of Things and automotive chips. It includes a zero current detector circuit that dynamically modifies the offset voltage, which can detect the inductor current when the buck circuit is operating in DCM mode. By turning off the power transistor in time, the control loss of the buck circuit can be reduced to improve efficiency. The proposed buck converter is designed using 0.18μm standard CMOS process. When a 12V standard input voltage is used to generate a 5V output voltage, the minimum inductor current can reach about 100uA when the low power transistor is turned off when the load current is in the light load range of 1mA-100mA, and the maximum efficiency can be achieved at light load of 93.7%.

A compact and wide-stopband filtering power divider (FPD) based on a single shielded circular patch resonator (SCPR) is presented in this paper. The SCPR is first introduced, which consists of a circular patch resonator loaded with a center metal via and a ring of shielding metal vias. When the TM₀₀ mode resonates, the half-mode SCPR (HMSCPR) and the quarter-mode SCPR (QMSCPR) obtained by dividing the full-mode SCPR (FMSCPR) with multiple slots have the same resonant frequency. Notedly, as the size of the resonator decreases, some higher-order modes are correspondingly suppressed. By combining an HMSCPR and two QMSCPRs, a compact second-order FPD with improved stopband performance can be realized. The good isolation between output ports can be achieved by loading three isolation resistors at the slots of two adjacent QMSCPRs. A prototype is designed, simulated, and measured to verify the proposed method.

This article presents a second-order cascaded integrator feedforward (CIFF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) reusing a dynamic amplifier. The proposed NS architecture uses a gain-optional floating inverter amplifier (FIA) and a sampling-before-integration technique to realize sharp noise transfer function (NTF) with minor extra capacitance. Implemented in 180-nm CMOS technology, the proposed NS-SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 88.6 dB over a sampling frequency of 1.6 MHz and an oversampling rate (OSR) of 16 while consuming only 250 µW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 171.6 dB, proving the proposed ADC fulfils considerable performance with both high resolution and low power consumption.

In this paper, a multi-objective optimization strategy is proposed for the design of high-density low-noise motors. The approach considers efficiency and computational accuracy and uses a wide-frequency-domain multi-operating-condition electromagnetic vibration source as the objective function. The first step is to identify the wide-speed multi-operating-condition vibration source of the motor using the unit-force-wave response method. Then, a multi-objective optimization model of high-density low-noise motors is established by combining electromagnetic design objectives to create a mapping relationship between the electromagnetic noise source and the structural parameters. This method optimizes a 48-slot 8-pole IPMSM for suppression in electric vehicles. The amplitude of the vibration source of the prototype is reduced by 80.73% and 85.48%, respectively, while the average torque remains unchanged. The vibration acceleration of the motor is significantly suppressed under the wide frequency domain multi-operating conditions. This paper provides technical support and design references for engineering applications.

This paper proposes a directly coupled instrumentation amplifier (IA) for EEG signal acquisition. By integrating both chopping and auto-zeroing (AZ) techniques, an offset and 1/f noise control loop (OFC) structure is proposed. Furthermore, a Capacitive Impedance Boost Loop (CIBL) configuration is presented to augment the input impedance within the EEG frequency band. Using the Common-Mode Biasing Circuit, the common mode rejection ratio (CMRR) of the circuit is improved. Fabricated in a 180-nm CMOS process, the prototype IA has the input-referred noise of 0.12 µV_rms from 0.01 Hz to 100 Hz. The proposed IA achieves high-input impedances of 4.14 GΩ at 20 Hz , and CMRR of 133.1 dB at 70 Hz.

Approximate computing stands as a highly promising approach in curbing power consumption and enhancing energy efficiency in error-tolerant applications, such as image processing and neural networks. This brief introduces two unsigned approximate multiplier designs: MUL1, tailored for high-precision applications, and MUL2, optimized for low-power usage. Furthermore, we propose Approximate N-4 compressors, which are devised based on input reordering circuits, along with a novel approximate 4-2 compressor that align positive and negative approximations for input patterns sharing the same probability. These proposed approximate multipliers have been synthesized using 40nm technology, demonstrating remarkable improvements. In comparison to the exact multiplier, the first proposed multiplier boasts an 84.98% enhancement in the power-delay-area product (PDAP), while the second multiplier achieves an even more significant improvement of 97.22% in this parameter.

A low-profile wideband dual-polarized antenna with nonuniform metasurface is proposed for 2G/3G/4G/IMT applications. The proposed antenna maintains broad bandwidth and stable gain but has a low profile of only 0.17λ₀ at 2.0 GHz, which contributes to the metasurface designed above the radiator. The nonuniform circular elements of the metasurface are set to reduce the coupling between each element, thus stable radiation patterns and low cross-polarization levels can be realized. The test results show a wide impedance bandwidth range from 1.4 GHz to 2.79 GHz (66.3%) for |S₁₁| < -10 dB and high isolation is more than 27 dB. The measured stable gain is 9±1 dBi. In the entire frequency band, stable radiation patterns are achieved with low cross-polarization levels below -18 dB.

This brief presents a fully integrated automatic impedance-matching RF energy harvesting system that automatically compensates for variations at the antenna-rectifier interface. The control loop is fully integrated on-chip with a low-voltage, low-power design. The design is fabricated in 0.18-μm CMOS technology, and the active chip area is 0.064 mm². The sensitivity optimized by impedance tuning can be improved to more than -30.5 dBm for 0.7 V output at varied initial mismatches, leading to a maximum increase in sensitivity of 5 dB. The control circuit's power consumption is only 2.4 nW, and the minimum supply voltage is 416 mV.

A Cascaded hybrid Fibonacci DC-DC converter with interleaved clock for DC grid is proposed. A hybrid Fibonacci stage is connected in series and the interleaved clock is applied. The modified converter is proposed by using two inductors in place of two switches of a typical X3 Fibonacci converter. By this modification, the converter achieved up to 20 of conversion rate (CR) at duty ratio of D

In this paper, we proposed a 0.98-ppm/°C, high power supply rejection (PSR), low-noise and curvature-compensated bandgap reference with a resistor-less low-pass filter in 0.18-µm CMOS process. One prominent feature of the circuit is a low-temperature coefficient (TC) measuring less than 1-ppm/°C, achieved through the implementation of high-order curvature compensation. Another notable enhancement is the incorporation of a resistor-less low-pass filter, which effectively improves the PSR and noise performance at medium and high frequencies. Experimental results indicate that the circuit is able to realize an average output reference voltage of 1.21V @4V and an average low TC of 0.98-ppm/°C @ -35°C-135°C at different corners. In addition, AC simulation results show that the circuit has a high PSR over the full frequency range and is capable of achieving PSR of -143.7 dB@10Hz, -90.1 dB@100KHz, and -134.0dB @100MHz. The output noise of the circuit measures 7.73nV/sqrtHz @10Hz, 30.60pV/sqrtHz @10KHz, and 11.75pV/sqrtHz @1MHz.

In this study, a novel noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) architecture is proposed, incorporating a noise transfer function (NTF) strengthening method (NSM). The order of NTF is strengthened by using an extra capacitive digital-to-analog converter (CDAC) and a cascaded Finite Impulse Response-Infinite Impulse Response (FIR-IIR) filter. The prototype converter uses an 8-bit split capacitor CDAC. The NSM is implemented on an NS SAR ADC in 40nm process technology, achieving an Effective Number of Bits (ENOB) of 16.6 bits at an effective bandwidth of 200 kHz with an oversampling ratio (OSR) of 32 and has been validated over process-voltage-temperature (PVT). The proposed ADC consumes 1.32 mW at a 1.1V supply voltage which occupies an active area of 0.0903 mm². The Schrier figure-of-merit (FoM) of 182.8 dB is obtained.

This paper presents a hardware-efficient delay ergodic cellular automaton gene-protein network model. It is shown that the presented model can reproduce the occurrence mechanism of one of the most typical nonlinear phenomena (supercritical Hopf bifurcation) of a mathematical gene-protein network model. Then the model is implemented by a field programmable gate array and experiments validate its operations. Furthermore, it is shown that the presented model is much more hardware-efficient compared to DSP-based and CPU-based gene-protein network models. It is then discussed that the presented model will be useful as a building block of a large-scale genome simulator for personalized medicine and drug discovery.

In this paper, an unconventional temperature sensor for harsh environments is proposed, which can be used for real-time measurement of temperature parameters in harsh environments such as high temperature and high pressure by embedding a complementary split resonant ring (CSRR) structure into a substrate integrated waveguide (SIW) structure. After experimental verification, the temperature sensitivity of the sensor is up to 401.2 kHz/°C, and the quality factor is still up to 2728.6 at 850°C, which effectively solves the problem of weakening or even annihilating the characteristic signals of wireless sensors at high temperatures. The sensor has the advantages of small size, high structural strength and high temperature corrosion resistance.

Physical Unclonable Functions(PUF) is a kind of hardware security primitive which is vulnerable to machine learning attacks. This work proposed a structural adjustment method based on Arbiter PUF(APUF), with the Strict Avalanche Criterion (SAC) as a guideline, improves the SAC property by leading multiple arbiters to obfuscation circuits at intermediate positions; quantitative analysis of SAC property by optimization method leads to the best placement of arbiters, which improves the utilization of resources. FPGA experiment results show that the proposed method significantly improves PUF’s resistance to machine learning attack such as logistic regression, evolutionary strategies and deep neural networks, and requires lower hardware resources overhead compared to other similar APUF based schemes with the same attack resistance.

In recent years, the use of metasurface to reduce radar cross section has been paid much attention with the rapid development of detection and stealth technology. In this paper, a 2-bit coding metasurface has been designed to realize broadband of Radar Cross Section (RCS) reduction. The designed metasurface consists of four units “00”, “01”, “10”, “11”. Then, Genetic Algorithm (GA) and Antenna Array Theory are used to optimize the arrangement of elements on the metasurface to obtain the optimal scattering characteristics. The measured result coincides with the simulated results. The RCSr curves of simulation and experiment reach below -10dB in the broadband range of 4.4-16.3GHz almost simultaneously. Compared with the metal plate, the beam manipulation capability of this 2-bit digital metasurface is obviously enhanced.

We conducted a study on the frequency dependence analysis of soft error rates using the test circuit composed of scan flip-flops (FFs) and inverters. By irradiating the circuit with alpha particles while the clock was running, soft error rates were measured. During alpha-particle irradiation, soft errors caused by inverters were almost negligible. Soft errors caused by FFs decreases as the operating frequency increases. On the other hand, during Ar irradiation, soft error rate was nearly constant with varying frequency. This is because, the increase in soft errors caused by inverters was roughly equal to the decrease in soft errors caused by FFs unlike alpha-particle irradiation.

This letter presents a fully monolithic microwave-integrated circuit (MMIC) substrate integrated waveguide (SIW) filter using integrated passive device (IPD) technology for Q-band applications. It is challenging to implement an SIW bandpass filter (BPF) at the chip level due to the complex process rules of chip processing. A possible solution is to use multiple TE101 mode SIW resonators to build a BPF via magnetic coupling. However, this layout method can easily cause a larger chip aspect ratio, which is not conducive to the chip’s reliability. To this end, the proposed SIW filter adopts four SIW resonators to form a highly selective BPF through planar stacking. Measurement results show that the minimum insertion loss of the proposed SIW filter is 3.07 dB, and fractional BW (FBW) of 4.4 % with a compact size of 0.199λ₀², including pad, which is among the best compared to previously reported SIW chip BPFs.

True random number generator (TRNG) is the important hardware security primitive for modern internet of things (IoT) devices, while the entropy source (ES) serves as the most crucial component for TRNG. This paper explores the NAND-XOR ring oscillators (NXROs) structure to design a novel ES architecture for TRNG. The basic principle of the ES is to add a self-feedback NAND gate in XOR RO to generate a high-frequency signal, so as to apply the signal to induce a high-frequency change of XOR RO oscillation states and thus to achieve a more significant amplification for random clock jitter. In addition, our NXRO has a higher oscillation frequency and min-entropy than traditional ROs. We implement a TRNG with the new NXRO ES unit on both Xilinx Spartan-6 and Atrix-7 FPGAs. Our experiment results demonstrate that compared with the state-of-the-art TRNGs, the new TRNG achieves a higher throughput and lower hardware overhead in generating true random numbers successfully passing the NIST test and AIS31 test without post-processing.

The bilateral filtering algorithm has broad application in image denoising. However, its complex computational and high bandwidth requirements for image data transmission have been limiting factors in its processing speed. This brief presents a high-throughput hardware architecture designed for the bilateral filtering algorithm, supporting images of arbitrary resolution and three convolution window sizes. This architecture reduces the computational through approximation calculations and enhances throughput for high-definition image processing via a data prefetch strategy. Additionally, we introduce a cost-effective MAC unit that minimizes critical path delays and area consumption. In terms of hardware implementation, even on a low-cost Xilinx Zynq-7000 FPGA platform can process 1024×1024 resolution images at over 160 frames per second, with a maximum working frequency of 192 MHz.

A multi-load wireless charging platform based on the principle of magnetic coupling resonant wireless power transfer (MCR-WPT) is proposed in this paper. The platform can simultaneously supply power to multiple receivers with different operating frequencies and each load is independent of the others loads. The system consists of a multi-frequency composite current source, a planar transmitter coil, an LC source multi-frequency tuning network, and several receivers operating at different frequencies. The mutual interference caused by cross-coupling and frequency cross-talk when multiple receivers are charging at the same time was analyzed. A load-independent principle to overcome these interferences was provided in the paper. Finally, a dual-frequency multi-load wireless charging experimental platform was built and measured. The well consistency between the experimental results and the theoretical analysis shows the effectiveness of the design method.

A novel dual-band high-gain shared-aperture antenna with a large frequency ratio is proposed in this letter. This antenna consists of two layers. Based on the different electromagnetic characteristics at two bands, these two layers can be used to form an Fabry-Perot cavity antenna (FPCA) in the microwave band and an folded transmitarray (FTA) in the millimeter-wave band. By integrating the FPCA into the FTA, we achieve a large frequency ratio of 8.6. A novel feed configuration with a horn in the center and a patch array along the edge is designed. Through the feed configuration based on FPCA and FTA, our shared-aperture antenna achieves higher aperture efficiency at dual bands compared with other similar works. An antenna prototype operating at both 3.5 GHz and 30 GHz bands is designed, fabricated and measured. Measurements show that the peak realized gain is 11.9 dBi at 3.5 GHz and 26.2 dBi at 30 GHz, respectively. The aperture efficiency can reach to 82% at the S band and 30% at the Ka band.

Beat-frequency ADCs emerged as a good choice for applications where low power consumption is important. However, there is a tradeoff between circuit power/area and quantization resolution. An Internal-states Beat-frequency ADC with subcircuit sharing is proposed to improve resolution while reducing the tradeoff. It was observed that SNDR/ENOB were improved by an average of 6.72dB/1.14bits by using the internal-states analysis without increasing system-wide area/power by means of the subcircuit sharing design method, thus alleviating the previously existing tradeoff.

An accurate and efficient electromagnetic (EM) modeling approach based on Neuro-space mapping (Neuro-SM) is proposed for substrate integrated suspension line (SISL) devices. A new coarse model containing 1 layer of dielectric plates, 2 layers of metal plates and 2 air cavities are developed to accelerate EM model simulation speed. To improve EM model accuracy, a parameter mapping network and a frequency mapping network are added into the structure. The EM responses of the SISL devices are taken as the fine model, while the proposed coarse model and two mapping networks are considered as the advanced Neuro-SM model. A three-step training process is developed to reduce errors between the fine and Neuro-SM model. The reasonable Neuro-SM model structure and efficient training algorithm greatly simplify the SISL device modeling process and further shorten the SISL device design cycle. The experimental results of a low-pass filter with SISL structure show that the training and test errors of the proposed model are 1.1% and 1.3%, which proves that the established model could accurately represent the characteristic of the SISL device.

In this paper, a family of zero voltage switching (ZVS) buck/boost converters with positive common rail (PCRBBC) is proposed for the PMSM sensorless driving system in electric vehicles. The proposed family of PCRBBCs includes more than 12 topologies with coupled LC or LD auxiliary circuits. Their special characteristics are the common positive connection between input and output ports, ZVS conditions, and a variety of different topologies to be chosen. The operation principle, soft-switching realization limit, application conditions, design guidance of proposed ZVS PCRBBCs are analyzed. Finally, an experimental prototype is built to verify the correctness and validity of the proposed soft-switching topologies.

This letter proposes a spring pendulum piezoelectric and electromagnetic vibration energy harvesting (SP-PEVEH) system. The SP-PEVEH system consists of a spring pendulum harvester and an interface circuit. The spring pendulum harvester can simultaneously generate energy through piezoelectric and magneto-electric transducers. Additionally, the spring pendulum harvester has the capability to harvest multidirectional vibration energy. The interface circuit can transfer energy from the harvesters to the storage. The maximum power point tracking (MPPT) control is also implemented to achieve efficient energy conversion. The experimental results reveal that with a resonant frequency vibration of 26.4 Hz and a maximum 1.5 m/s² acceleration, the SP-PEVEH system can generate 11.63 mW power. As compared with a conventional interface circuit without MPPT control, the output power is increased by 676%.

Weak resistive defects in standard cells exhibit subtle electrical behaviour that may lead to test escapes, thereby compromising the reliability of integrated circuits. Fault analysis data has shown that the presence of weak defects in specific cells can cause variations in output timing when multiple transitions occur on the inputs, as opposed to a single transition. However, existing delay test generation tools do not account for the effect of multiple input switching (MIS). In this paper, the effects of MIS on defect detection and timing analysis are analyzed and a multi-transition delay test method is proposed to further expose and detect cell internal defects. In addition to sensitizing the selected paths, the new test pattern attempts to maximize the off-path input transitions, thus increasing the propagation delay of the selected paths or the proportion of incremental delay introduced by the defects. The simulation results on ISCAS benchmark circuits show that the proposed method achieves a maximum of 8.73% and an average of 5.99% defect coverage gain compared to the existing delay tests that based on single input switching schemes.