In this paper the three dimensional (3-D) effect on CMOS latch-up is modeled using a graphical technique based on the fundamental principle of "charge neutrality or its current continuity equivalent" in the base region of parasitic transistors involved in latch-up. The graphical generation of the complete latch-up I-V characteristic requires as an input the SPICE parameters of the relevant bipolar and MOS transistors, the values of shunt resistances and the reverse current-voltage characteristic of the well-substrate junction. The infiuence of the MOS transistor shunting the parasitic bipolar transistors has received special attention. The nonideal scaling of the parasitic resistances has been observed to be the most crucial parameter determining the 3-D nature of the device. The proposed model is validated with test-structures fabricated in 2 µm bulk CMOS technology at and above room temperature. SAFE space map is constructed with width W as a parameter.