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[Author] Akihiko YAMADA(2hit)

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  • The Two-Dimensional Lapped Hadamard Transform

    Shogo MURAMATSU  Akihiko YAMADA  Hitoshi KIYA  

     
    PAPER

      Vol:
    E81-A No:8
      Page(s):
    1542-1549

    In this paper, a two-dimensional (2-D) binary-valued (BV) lapped transform (LT) is proposed. The proposed LT has basis images which take only BV elements and satisfies the axial-symmetric (AS) property. In one dimension, there is no 2-point LT with the symmetric basis vectors, and the property is achieved only with the non-overlapping basis which the Hadamard transform (HT) has. Hence, in two dimension, there is no 22-point separable ASLT, and only 2-D HT can be the 22-point separable AS orthogonal transform. By taking non-separable BV basis images, this paper shows that a 22-point ASLT can be obtained. Since the proposed LT is similar to HT, it is referred to as the lapped Hadamard transform (LHT). LHT of larger size is shown to be provided with a tree structure. In addition, LHT is shown to be efficiently implemented by a lattice structure.

  • A Bit-Operation Algorithm of the Median-Cut Quantization and Its Hardware Architecture

    Shogo MURAMATSU  Hitoshi KIYA  Akihiko YAMADA  

     
    PAPER

      Vol:
    E83-A No:2
      Page(s):
    320-328

    In this paper, an algorithm of the median-cut quantization (MCQ) is proposed. MCQ is the technique that reduces multi-valued samples to binary-valued ones by adaptively taking the median value as the threshold. In this work, the search process of the median value is derived from the quick-sort algorithm. The proposed algorithm searches the median value bit by bit, and samples are quantized during the search process. Firstly, the bit-serial procedure is shown, and then it is modified to the bit-parallel procedure. The extension to the multi-level quantization is also discussed. Since the proposed algorithm is based on bit operations, it is suitable for hardware implementation. Thus, its hardware architecture is also proposed. To verify the significance, for the application to the motion estimation, the performance is estimated from the synthesis result of the VHDL model.