With the development of LSI technologies, conventional circuit simulation using only single type of method has become unsatisfactory, i.e. circuit-level analysis based on device model spends much simulation time and relaxation methods have the problems on their accuracy. Therefore, it is necessary to develop the better methods to realize both high-speed and good accuracy. In this paper, a mixed-mode circuit-timing simulation method has been studied. It uses a new kind of automatic circuit partition approach--dynamic circuit partition process based on checking coupling factors between circuit nodes at every time point for better convergence. This method is based on examining the characteristic of circuit equations rather than circuit topology or function blocks. A mixed-mode simulation program--MMAPC for transient analysis of CMOS large-scale circuit has been developed and some simulation examples have been performed. The results show that MMAPC can be more than two orders of magnitude faster than a standard" circuit-level simulator (SPICE-like) while providing comparable waveform accuracy, and has better convergence property than general timing-level simulators.

In this paper we present an Overlapped Block Gauss-Seidel (OBGS) algorithm for the solution of large scale LSEs (Linear System of Equations) based on array architecture which we have already proposed. Better partitioning for processor array usually requires (1) balanced block size, and (2) minimum coupling between blocks for better convergence. These conditions can well be satisfied by overlapping some variables in computation algorithm. The mathematical implication of overlapped partitioning is discussed at first, and some examples show the effectiveness of OBGS algorithm. Conclusion points out that the convergence properties can well be improved by proper choice of overlapped variables. An efficient algorithm is given for choosing block and variables in order to realize above conditions.

A reconfigurable array for solving linear system of equations (LSE) by LU-decomposition method is considered. It has nearly a half of the number of processing elements (PE) and I/O terminals with reduced computation time compared with known conventional array structures.