This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

A bottleneck identification methodology is proposed for the performance-oriented design of shared-bus multiprocessors, which are composed of several major subsystems (e.g. off-chip cache, bus, memory, I/O). A subsystem with the longest access time per instruction is the one that limits processor performance and creates a bottleneck to the system. The methodology also facilitates further refined analysis on the access time of the bottleneck subsystem to help identify the causes of the bottleneck. Example performance model of a particular shared-bus multiprocessor architecture with separate address bus and data bus is developed to illustrate the key idea of the bottleneck identification methodology. Accessing conflicts in subsystems and DMA transfers are also considered in the model.

This paper presents a server-based approach to maintaining software integrity for all computer classroom workstations. The approach takes several advantages: (1) applicable to the FAT (file allocation table) and NTFS file systems, (2) renovating all workstations to workable state, (3) quickly adding or removing software systems to or from all workstations for teachers conducting new courses, and (4) automatically changing computer name and IP (Internet Protocol) address to an appointed one. The basic concept of the server-based maintenance approach is to install whole software systems, including operating system and applications, on a normal workstation, to make one image copy of the workstation's hard disk and store it onto network server, and to restore the image file from the server to the remaining workstations. In order to change computer name and IP automatically, this paper presents a searching heuristic for finding their locations in the image file. The heuristic is modified from Boyer-Moore (BM) algorithm and can improve the BM algorithm's performance over 9%.

Evaluating analytically computer architecture performance is mostly cheap and quick. However, existing analytical performance evaluation techniques usually have a difficult and time-consuming modeling process. Moreover, existing techniques do not support well the capability for finding the bottleneck and its cause of a target system being evaluated. To address the above problems and to enhance analytical performance evaluation technology, in this paper we propose a software tool that accepts system models described in a specification language, generating an executable program that performs the actual performance evaluation. The whole approach is built on a subsystem-oriented performance evaluation tool, which is, in turn, based on a formal subsystem-oriented performance evaluation technique and a subsystem specification language.