This paper presents a 6th-order quadrature bandpass delta sigma AD modulator (QBPDSM) with 2nd-order image rejection using dynamic amplifier and noise coupling (NC) SAR quantizer embedded by passive adder for the application of wireless communication system. A novel complex integrator using dynamic amplifier is proposed to improve the energy efficiency of the QBPDSM. The NC SAR quantizer can realize an additional 2nd-order noise shaping and 2nd-order image rejection by the digital domain noise coupling technique. As a result, the 6th-order QBPDSM with 2nd-order image rejection is realized by two complex integrators using dynamic amplifier and the NC SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed QBPDSM in 90nm CMOS technology. Simulated SNDR of 76.30dB is realized while a sinusoid -3.25dBFS input is sampled at 33.3MS/s and the bandwidth of 2.083MHz (OSR=8) is achieved. The total power consumption in the modulator is 6.74mW while the supply voltage is 1.2V.

This paper presents a 3rd-order ΔΣAD modulator with noise coupling structure using the proposed passive adder embedded quantization noise shaping (QNS) SAR quantizer. QNS SAR quantizer can feedback shaped quantization noise and realize an additional 1st-order noise shaping by noise coupling technique. As a result, the 3rd-order noise coupled ΔΣAD modulator is realized by two integrators with ring amplifier and the QNS SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 81.05dB is achieved while a sinusoid -4.32dBFS input is sampled at 100MS/s and the bandwidth is BW=3.125MHz. The total power consumption in the modulator is 4.58mW while the supply voltage is 1.2V.

A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 95.70dB is achieved while a sinusoid -1dBFS input is sampled at 60MS/s for the bandwidth is BW=470kHz. The power consumption of the analog part in the modulator is 1.67mW while the supply voltage is 1.2V.