The rapid prototyping of a mixed-signal system-on-chip (SoC) has been enabled by reusing predesigned intellectual properties (IPs) and by integrating newly designed IP into the top design of SoC. The IPs have been designed on various hardware description levels, which leads to challenges in simulations that evaluate the prototyping. One traditional solution is to convert these heterogeneous IP models into equivalent models, that are described in a single description language. This conversion approach often requires manual rewriting of existing IPs, and this results in description loss during the model projection due to the absence of automatic conversion tools. The other solutions are co-simulation/emulation approaches that are based on the coupling of multiple simulators/emulators through connection modules. The conventional methods do not have formal theoretical backgrounds and an explicit interface for integrating the simulator into their solutions. In this paper, we propose a general co-simulation approach based on the high-level architecture (HLA) and a newly-defined programming language interface for interoperation (PLI-I) between heterogeneous IPs as a formal simulator interface. Based on the proposed PLI-I and HLA, we introduce formal procedures of integration and interoperation. To reduce integration costs, we split these procedures into two parts: a reusable common library and an additional model-dependent signal-to-event (SE) converter to handle differently abstracted in/out signals between the coupled IPs. During the interoperation, to resolve the different time-advance mechanisms and increase computation concurrency between digital and analog simulators, the proposed co-simulation approach performs an advanced HLA-based synchronization using the pre-simulation concepts. The case study shows the validation of interoperation behaviors between the heterogeneous IPs in mixed-signal SoC design, the reduced design effort in integrating, and the synchronization speedup using the proposed approach.

IoT devices operate with a battery and have embedded firmware in flash memory. If the embedded firmware is not kept up to date, there is a possibility of problems that cannot be linked with other IoT networks, so it is necessary to maintain the latest firmware with frequent updates. However, because firmware updates require developers and equipment, they consume manpower and time. Additionally, because the device must be active during the update, a low-power operation is not possible due to frequent flash memory access. In addition, if an unexpected interruption occurs during an update, the device is unavailable and requires a reliable update. Therefore, this paper aims to improve the reliability of updates and low-power operation by proposing a technique of performing firmware updates at high speed. In this paper, we propose a technique to update only a part of the firmware stored in nonvolatile flash memory without pre-processing to generate delta files. The firmware is divided into function blocks, and their addresses are collectively managed in a separate area called a function map. When updating the firmware, only the new function block to be updated is transmitted from the host downloader, and the bootloader proceeds with the update using the function block stored in the flash memory. Instead of transmitting the entire new firmware and writing it in the memory, using only function block reduces the amount of resources required for updating. Function-blocks can be called indirectly through a function map, so that the update can be completed by modifying only the function map regardless of the physical location. Our evaluation results show that the proposed technique effectively reduces the time cost, energy consumption, and additional memory usage overhead that can occur when updating firmware.