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[Author] Dong-Gyu KIM(2hit)

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  • Numerical Implementation of Generalized Monopulse Estimation with Measured Subarray Patterns

    EunHee KIM  Dong-Gyu KIM  

     
    PAPER-Electromagnetic Theory

      Vol:
    E98-C No:4
      Page(s):
    340-348

    Monopulse is a classical technique for radar angle estimation and still adopted for fast angle estimation in phased array antenna. The classical formula can be applied to a 2-dimentional phased array antenna if two conditions---the unbiasedness and the independence of the azimuth and the elevation estimate---are satisfied. However, if the sum and difference beams are adapted to suppress the interference under jamming condition, they can be severely distorted. Thus the difference beams become highly correlated and violate the conditions. In this paper, we show the numerical implementation of the generalized monopulse estimation using the distorted and correlated beams, especially for a subarray configured antenna. Because we use the data from the measured subarray patterns rather than the mathematical model, this numerical method can be easily implemented for the complex array configuration and gives good performance for the uncertainty of the real system.

  • Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications

    Joonho LIM  Dong-Gyu KIM  Soo-Ik CHAE  

     
    PAPER-Integrated Electronics

      Vol:
    E82-C No:4
      Page(s):
    646-653

    We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.