Vehicular Ad hoc Network (VANET) is an important part of the Intelligent Transportation System (ITS). VANETs can realize communication between moving vehicles, infrastructures and other intelligent mobile terminals, which can greatly improve the road safety and traffic efficiency effectively. Existing studies of vehicular ad hoc network usually consider only one data transmission model, while the increasing density of traffic data sources means that the vehicular ad hoc network is evolving into Heterogeneous Vehicular Network (HetVNET) which needs hybrid data transmission scheme. Considering the Heterogeneous Vehicular Network, this paper presents a hybrid transmission MAC protocol including vehicle to vehicle communication (V2V) and vehicle to infrastructure communication (V2I/I2V). In this protocol, the data are identified according to timeliness, on the base of the traditional V2V and V2I/I2V communication. If the time-sensitive data (V2V data) fail in transmission, the node transmits the data to the base station and let the base station cooperatively transmit the data with higher priority. This transmission scheme uses the large transmission range of base station in an effective manner. In this paper, the queueing models of the vehicles and base station are analyzed respectively by one-dimensional and two-dimensional Markov Chain, and the expressions of throughput, packet drop rate and delay are also derived. The simulation results show that this MAC protocol can improve the transmission efficiency of V2V communication and reduce the delay of V2V data without losing the system performance.

In recent years, dramatic improvements have been made to computer hardware. In particular, the number of cores on a chip has been growing exponentially, enabling an ever-increasing number of processes to be executed in parallel. Having been originally developed for single-core processors, database (DB) management systems (DBMSs) running on multicore processors suffer from cache conflicts as the number of concurrently executing DB processes (DBPs) increases. Therefore, a cache-efficient solution for arranging the execution of concurrent DBPs on multicore platforms would be highly attractive for DBMSs. In this paper, we propose CARIC-DA, middleware for achieving higher performance in DBMSs on multicore processors, by reducing cache misses with a new cache-conscious dispatcher for concurrent queries. CARIC-DA logically range-partitions the dataset into multiple subsets. This enables different processor cores to access different subsets by ensuring that different DBPs are pinned to different cores and by dispatching queries to DBPs according to the data-partitioning information. In this way, CARIC-DA is expected to achieve better performance via a higher cache hit rate for the private cache of each core. It can also balance the loads between cores by changing the range of each subset. Note that CARIC-DA is pure middleware, meaning that it avoids any modification to existing operating systems (OSs) and DBMSs, thereby making it more practical. This is important because the source code for existing DBMSs is large and complex, making it very expensive to modify. We implemented a prototype that uses unmodified existing Linux and PostgreSQL environments, and evaluated the effectiveness of our proposal on three different multicore platforms. The performance evaluation against benchmarks revealed that CARIC-DA achieved improved cache hit rates and higher performance.