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[Author] Gianpaolo PRINA(1hit)

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  • A Selective Invalidation Strategy for Cache Coherence

    Cosimo Antonio PRETE  Gianpaolo PRINA  Luigi RICCIARDI  

     
    LETTER-Computer Hardware and Design

      Vol:
    E78-D No:10
      Page(s):
    1316-1320

    The overall performance of a shared-memory, common bus multiprocesser system can be seriously affected by useless coherence-related actions. This occurs, in particular, when a private data block of a process becomes resident in more than one cache as a consequence of the migration of the owner process. We introduce a hardware solution to eliminate these useless shared copies, and show how this technique can be applied to a specific coherence protocol. Two extreme workload conditions are properly selected to evaluate the performance of a multiprocessor system.