In this paper, an algorithm for Boolean factoring is presented. The algorithm is based on a technique of rectangle covering. A distinctive feature of the algorithm is that no minimization step is required to achieve Boolean factoring. The method for computing Boolean products rests on the concepts of super-product, extended kernel and extended co-kernel-cube matrix. Results of a comparison with the algorithms GOOD_FACTOR and QUICK_FACTOR implemented in SIS are presented. SIS is a program for logic synthesis developed at the University of Berkeley. All performed tests indicate that the proposed algorithm realizes a good tradeoff between factoring quality and computing time.

The present paper is concerned with an algorithm for the minimization of multiple-valued input, binary-valued output functions. The algorithm is an extension to muitiple-valued logic of an algorithm for the minimization of ordinary single-output Boolean functions. It is based on a local covering approach. Basically, it uses a "divide and conquer" technique, consisting of two steps called expansion and selection. The present algorithm preserves two important features of the original one. First, a lower bound on the number of prime implicants in the minimum cover of the given function is furnished as a by-product of the minimization. Second, all the essential primes of the function are identified and selected during the expansion process. That usually improves efficiency when handling functions with many essential primes. Results of a comparison of the proposed algorithm with the program ESPRESSO-IIC developed at Berkeley are presented.

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

Methods usually employed for carrying out division in logic are based on algebraic or Boolean techniques. Algebraic division is fast but results may be less than optimal. Boolean division will yield better results but generally it is much slower because a minimization step is required. In [4], Kim and Dietmeyer proposed a new type of division, called extended algebraic division, and described a heuristic algorithm for it. A feature is that, unlike Boolean division, it does not require a minimization step. The present paper is concerned with an efficient algorithm for exact extended algebraic division. The algorithm was developed within the SIS environment, a program for logic synthesis developed at U.C. Berkeley. Experiments on factoring PLA's demonstrate a significant improvement in quality with a reasonable increase in run time.