This paper presents a low-power implementation scheme of interpolation FIR filters using distributed arithmetic (DA). The key idea of the proposed scheme involves look-up tables generating only nonnegative values. Thus, the proposed scheme can minimize the dynamic power consumption of interpolation FIR filters using DA without additional hardware. When used for implementing a pulse shaping filter for CDMA2000 mobile stations, the proposed filter not only has almost the same hardware complexity as the conventional one; it also has approximately 43% reduced power consumption.

The performance of an analog winner-take-all (WTA) circuit is affected by the corner error and the offset error. Despite the fact that the corner error can be reduced with large transconductance of the transistor, the offset error caused by device mismatch has not been completely studied. This paper presents the complete offset error analysis, and proposes low offset design guidelines and an offset cancellation scheme. The experimental results show good agreement with the theoretical analysis and the drastic improvement of the offset error.

Scientific computations for diffusion equations and ANNs (Artificial Neural Networks) are data intensive tasks accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. Thus, this type of tasks naturally maps onto SIMD (Single Instruction Multiple Data stream) parallel processing with distributed memory. This paper proposes a high performance acceleration processor of which architecture is optimized for scientific computing using diffusion equations and ANNs. The proposed architecture includes a customized instruction set and specific hardware resources which consist of a control unit (CU), 16 processing units (PUs), and a non-linear function unit (NFU) on chip. They are effectively connected with dedicated ring and global bus structure. Each PU is equipped with an address modifier (AM) and 16-bit 1.5 k-word local memory (LM). The proposed processor can be easily expanded by multi-chip expansion mode to accommodate to a large scale parallel computation. The prototype chip is implemented with FPGA. The total gate count is about 1 million with 530, 432-bit embedded memory cells and it operates at 15 MHz. The functionality and performance of the proposed processor is verified with simulation of oil reservoir problem using diffusion equations and character recognition application using ANNs. The execution times of two applications are compared with software realizations on 1.7 GHz Pentium IV personal computer. Though the proposed processor architecture and the instruction set are optimized for diffusion equations and ANNs, it provides flexibility to program for many other scientific computation algorithms.

This letter proposes a mismatch insensitive switched-capacitor multiply-by-four (4X) amplifier using the voltage addition scheme. The proposed circuit provides 2-times faster speed and about half of silicon area when compared with the cascade of conventional 2X amplifiers. Monte-Carlo simulation results show about 15% gain accuracy improvement over the cascaded 2X- amplifiers.

This paper proposes a compact interpolation scheme dedicated to a 1-dimensional position sensitive detector (PSD) with an optical sensing pixel array. The pixels are divided into even- and odd-numbered groups and winner take all (WTA) circuits are provided to each of the groups. The simulated results show that the detecting step-width is reduced to the half of the original one after applying the interpolation scheme.

A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

Uncertainty within one-wavelength (λ) is inevitable in an ultrasound positioning system that measures the time of flight of ultrasound pulses especially when a simple comparator is used for pulse detection. This paper proposes a compensation scheme based on pulse period adjustment. The test results show that the proposed scheme efficiently eliminates the 1λ-deviation and provides improved distance measurement.

The cable length in wired serial data communication is limited because the limited bandwidth of a long cable introduces ISI (Inter Symbol Interference). A line equalizer can be used at the receiver to extend the channel bandwidth. This paper proposes a low-power and small-area analog adaptive line equalizer for 100-Mb/s operation on UTP (Unshielded Twisted Pair) cable up to 100 m. The proposed adaptive line equalizer is fabricated with 0.35-µm CMOS process, consumes 19 mW and occupies only 0.07 mm2 Measurement results show that the prototype can operate at data rate of 100 Mb/s on a 100-m cable and 155 Mb/s on a 50-m cable.

In a switched-capacitor (SC) circuit, the major block is an operational transconductance amplifier (OTA) designed in order to form a feedback loop. However, the OTA is the block that consumes most of the power in SC circuits. This paper proposes the use of a class-C inverter instead of the OTA in SC circuits and a corresponding switches configuration for extremely low power applications. A detailed analysis and design trade-offs are also provided. Simulation and experimental results show that sufficient performance can be obtained even though a class-C inverter is used. The second-order biquad filter and the second-order SC sigma-delta (ΣΔ) modulator based on a class-C inverter are designed. These circuits have been fabricated with a 0.35-µm CMOS process. The measurement results of the fabricated SC biquad filter show a 59-dB signal-to-noise-plus-distortion ratio (SNDR) for a 0.2-Vp-p input signal and 0.9-V dynamic ranges. The power consumption of the biquad filter is only 0.4 µW with a 1-V power supply. The measurement results of the fabricated ΣΔ modulator show a 61-dB peak SNR for a 1.6-kHz bandwidth with a sample rate of 200 kHz. The modulator consumes 0.8 µW with a 1-V power supply.