The maximum bit capacity of poly-Si loaded SRAM's is estimated, based on cell stability limits. When SRAM density increases, the voltage level of a storage node in the high state decreases more quickly because of MOS drain leakage current that flows in the poly-Si load; this can prevent regular cell operation. The poly-Si load resistance and the drain leakage current distribution are measured by using special 0.8-µm 1-Mb SRAM test chips. The maximum bit capacity is then calculated for low-power and high-speed SRAM's. The limit is 4 Mb for low-power SRAM's and 4 Gb for high-speed SRAM's.