The sharpness of the roll-off response of bandpass filters is a major concern for wireless communication systems. Bandpass filters with attenuation poles provide sharp roll-off. This paper investigates the performance of a ceramic comb-line filter with attenuation pole resonators (APRs), and studies the effects of the attenuation pole resonators on the filter response. The presented APRs are improved versions of previous ones and they are modeled here. The obtained results show that the length of APRs can be miniaturized via the loading capacitance. The resultant volume is about 400 mm3, which is very small comparing to coaxial type filters with the same attenuation rate in the stopband. With attenuation pole resonators added, skirt attenuation is greatly improved. Narrow bandwidth bandpass filters with attenuation poles in the stopband are designed and tested. Two designed examples demonstrate the flexibility of the attenuation pole resonator in the filter configuration. Experiments show good agreement with simulation results.

GaAs MMICs (Monolithic Microwave Integrated Circuits) reliability is a critical part of the overall reliability of the thermal solution in semiconductor devices. With MMICs reliability improved, GaAs MMICs failure rates will reach levels which are impractical to measure with conventional methods in the near future. This letter proposes a methodology to predict the GaAs MMICs reliability by combining empirical and statistical methods based on zero-failure GaAs MMICs life testing data. Besides, we investigate the effect of accelerated factors on MMICs degradation and make a comparison between the Weibull and lognormal distributions. The method has been used in the reliability evaluation of GaAs MMICs successfully.

As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.