A switching network construction scheme for a fast packet switching system, which is expected to provide multi-media services efficiently and economically, is proposed. The proposed packet switch has RAM as a shared buffer. Its access is assigned to input and output ports dynamically in order to fully utilize limited memory time. This enables packet switches to flexibly accommodate packet links having different bit-rates. An asynchronous data transfer technique is also incorporated into inter-switch links. This switching network can dynamically alter the inter-switch link speed, according to the demanded flow. The dynamism of this simple hardware contributes greatly to better packet transfer quality. This paper describes switch architecture, multi-stage packet switching network construction which can handle any combination of packet flow without centralized switch resource management, and simulated packet transport characteristics of a multi-stage switching network. The simulation results show that the proposed switching network gives good packet transport quality, in terms of packet delay and loss. Finally, the congestion mechanism is analyzed.