Author Search Result
[Author] Hideo MUKAI(1hit)
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A 286 mm2 256 Mb DRAM with
32 Both-Ends DQYohji WATANABE Hing WONG Toshiaki KIRIHATA Dasisuke KATO John K. DEBROSSE Takahiko HARA Munehiro YOSHIDA Hideo MUKAI Khandker N. QUADER Takeshi NAGAI Peter POECHMUELLER Peter PFEFFERL Matthew R. WORDEMAN Shuso FUJII
- PAPER-Memory
- Vol:
- E79-C No:7
- Page(s):
- 978-985
This paper descriles a 256 Mb DRAM chip architecture which provides up to 32 wide organization. In order to minimize the die sixe, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25µmCMOS technology. The chip measures 13.25mm21.55mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe(RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 . In addition, a 100 MHz32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output(EDO) cycle has been succssfully demonstrated.
