A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

Electro-thermal characteristics of the Si MOSFET in transient state are reported using a non-isothermal device simulator where both the transistor's self-heating and the thermal influence of its neighboring devices are duly taken into account. The thermal influence is estimated using a three-dimensional thermal simulator. Based on this set-up, we predict time-dependent electro-thermal characteristics of the Si MOSFET at gate switching and its drain breakdown conditions. We show that the time delay between the electrical response and the lattice temperature rise, is significant and thus can not be neglected. In addition, we found that avalanche and thermal breakdown characteristics largely depend on the slope of the drain input voltage.

The potential drop and the self-heating due to the contact resistance at the interface between silicide and silicon are incorporated in the device simulation for ESD protection devices. A transition region is provided at the interface and the resistivity is calculated by scaling the contact resistance by the length of the region. The power density used in the heat conductive equation is calculated by using the potential drop and the contact resistance in the transition region. The validity of the present approach is checked by the Monte Carlo simulations. Using the technique, influence of the contact resistance on self-heating in an ESD protection device with the grounded gate MOSFET structure is simulated.