In this paper, we discuss an IF image rejection system with variable bandwidth and center frequency. The system is consists of a pair of frequency mixers multiplied by the complex sinusoid and a complex analog filter. By employing the complex leapfrog structure using OTA-C configuration and the frequency transformation from the normalized LPF, the proposed system is capable of variable bandwidth and center frequency characteristics. SPICE simulations result more than 43 [dB] image rejection is achieved for 6 [kHz] and 12 [kHz] bandwidths at 50 [kHz] IF.

A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.