The search functionality is under construction.

Author Search Result

[Author] Hiroyuki MIYAUCHI(2hit)

1-2hit
  • Fault Tolerant Non-regular Digital Signal Processing Based on Computation Tree Block Decomposition

    Mineo KANEKO  Hiroyuki MIYAUCHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E77-A No:9
      Page(s):
    1535-1545

    In this paper, we present Branching Oriented System Equation based on-line error correction scheme for recursive digital signal processing. The target digital signal processing is linear and time-invariant, and the algorithm includes multiplications with constant coefficient, additions and delays. The difficulties of the algorithm-level fault tolerance for such algorithm without structural regularity include error distribution problem and right timing of error correction. To escape the error distribution problem, multiple fan-out nodes in an algorithm are specified as the nodes at which error corrections are performed. The Branching Oriented Graph and Branching Oriented System Equation are so introduced to formulate on-line correction schemes based on this strategy. The Branching Oriented Graph is treated as the collection of computation sub-blocks. Applying checksum code independently to each sub-block is our most trivial on-line error correction scheme, and it results in, with appropriate selection of error identification process, TMR in sub-block level. One of the advantages of our method is in the reduction of redundant operations performed by merging some computation sub-blocks. On the other hand, the schedulability of the system is an important issue for our method since our on-line error correction mechanism induces additional data dependencies. In this paper, the schedulability condition and some modifications on the scheme are also discussed.

  • A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space

    Mineo KANEKO  Hiroyuki MIYAUCHI  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E79-D No:12
      Page(s):
    1676-1689

    A systematic procedure to configure faulttolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed from a target regular algorithm and the transformation onto physical time-processor domain. The resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While it needs sophisticated connection scheme between processing elements to guarantee the fault-tolerance on communication links, the link complexity is possibly reduced by optimizing redundant operation scheme. Unconstrained and constrained link minimization problems are introduced, and the possibility and the constraints required for link complexity reduction are investigated.