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[Author] Hyeong-Cheol OH(3hit)

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  • Low-Cost Method for Recognizing Table Tennis Activity

    Se-Min LIM  Jooyoung PARK  Hyeong-Cheol OH  

     
    LETTER-Artificial Intelligence, Data Mining

      Pubricized:
    2019/06/18
      Vol:
    E102-D No:10
      Page(s):
    2051-2054

    This study designs a low-cost portable device that functions as a coaching assistant system which can support table tennis practice. Although deep learning technology is a promising solution to realizing human activity recognition, we propose using cosine similarity in making inferences. Our experiments show that the cosine similarity based inference can be a good alternative to the deep learning based inference for the assistant system when resources are limited.

  • Design of an OpenVG Hardware Rendering Engine

    Yong-Luo SHEN  Seok-Jae KIM  Sang-Woo SEO  Hyun-Goo LEE  Hyeong-Cheol OH  

     
    PAPER-Computer System

      Vol:
    E94-D No:12
      Page(s):
    2409-2417

    This paper introduces a hardware engine for rendering two-dimensional vector graphics based on the OpenVG standard in portable devices. We focus on two design challenges posed by the rendering engines: the number of vertices to represent the images and the amount of memory usage. Redundant vertices are eliminated using adaptive tessellation, in which the redundancy can be judged using a proposed cost-per-quality measure. A simplified edge-flag rendering algorithm and the scanline-based rendering scheme are adopted to reduce external memory access. The designed rendering engine occupies approximately 173 K gates and can satisfy real-time requirements of many applications when it is implemented using a 0.18 µm, 1.8 V CMOS standard cell library. An FPGA prototype using a system-on-a-chip platform has been developed and tested.

  • Pipelined Squarer for Unsigned Integers of Up to 12 Bits

    Seongjin CHOI  Hyeong-Cheol OH  

     
    LETTER-Computer System

      Pubricized:
    2017/12/06
      Vol:
    E101-D No:3
      Page(s):
    795-798

    This paper proposes and analyzes a pipelining scheme for a hardware squarer that can square unsigned integers of up to 12 bits. Each stage is designed and adjusted such that stage delays are well balanced and that the critical path delay of the design does not exceed the reference value which is set up based on the analysis. The resultant design has the critical path delay of approximately 3.5 times a full-adder delay. In an implementation using an Intel Stratix V FPGA, the design operates at approximately 23% higher frequency than the comparable pipelined squarer provided in the Intel library.