This paper describes a digital impedance controller (DIC) [1] for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23 Ω to 140 Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is 2.26% with RQ ranging from 23 Ω to 53 Ω, the same range covered by conventional scheme. The high resolution and wide range impedance control is implemented by using automatic gate voltage optimization. The amount of jitter caused by quantization error is 6.9 ps while 13.8 ps in conventional scheme. The data input valid window is 623 ps at 0.75200 mV and maximum eye open is 641 mV meaning about 10% improvement at 1.5 Gbps/pin DDR3 SRAM interface.

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 µm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.