The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4 V, the maximum operating speed changes by about 40–50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

A sub-mW current-reuse CMOS VCO is presented for wireless sensor network applications. In order to break the interdependence between the current consumption and the phase noise performance in the conventional current-reuse structure, a tail current source is added to the switching core in such a way that they are simultaneously switched during operation. With this, the current consumption can be maintained at a minimum level while the FET size can be optimally determined for large swing and good phase noise performances. The proposed VCO's advantage of achieving low phase noise at low current consumption is clearly demonstrated by simulations in comparison to the conventional structure. The proposed VCO is implemented in 0.13 µm CMOS. It dissipates 0.6 mW from 1.2 V supply. The measured phase noise at the output frequency of 2.28 GHz is -121 dBc/Hz at 1 MHz offset.

A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

An output load VSWR (voltage standing wave ratio) protection circuit for SiGe power amplifiers (PA) is presented by using the relatively low collector-emitter avalanche breakdown characteristic of SiGe HBT. Unlike the conventional diode-type switch, the new protection circuit completely eliminates the undesirable dc leakage current during the normal operation of the PA. Simulations and measurements show the proposed protection circuit enhances the ruggedness of the PA at harsh operating condition while it imposes only minor performance degradation at normal operating condition.

In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective junction area ratio in the bandgap reference, which significantly lowers the output spectral noise of the LDO. A low noise LDO with the area-efficient bandgap reference is implemented in 0.18 µm CMOS. An effective diode area ratio of 105 is obtained while the actual silicon area is saved by a factor of 4.77. As a result, a remarkably low output noise of 186 nV/sqrt(Hz) is achieved at 1 kHz. Moreover, the dropout voltage, line regulation, and load regulation of the LDO are measured to be 0.3 V, 0.04%/V, and 0.46%, respectively.