Bi-stable displays form the foundation of a novel and attractive LCD technology. From now on, images can be maintained on the LCD after driving voltages have been withdrawn from the electrodes. In low frame-rate applications such as e-books, e-labels, smartcards etc., this offers a major improvement in power consumption and battery life. However, bi-stable displays require high driving voltages and complex waveforms. Furthermore, the nature of some applications doesn't allow the use of relatively large passive components. This rules out more traditional approaches for high-voltage generation with external coils or capacitors. This paper describes the design of completely integrated and programmable high-voltage generators capable of generating output voltages up to 50 V out of a 3 V supply voltage. Features like 8-bit output voltage programmability and stabilisation were implemented to make this type of high-voltage generator suitable for bi-stable display drivers. Design aspects and simulation results are discussed, as well as measurements on prototype generators implemented in the 0.7 µm 100 V I2T100 technology from AMI Semiconductor.

A fully integrated 16-phase 8-branch Dickson charge pump is proposed and implemented to decrease the power dissipation due to parasitic capacitance at the bottom plate of the boost capacitor. By using the charge recycling concept, 87% of the power consumption related to parasitic capacitance is saved. In a 4-stage version of this charge pump, a maximum power efficiency of 41% is achieved at 35µA output current and 11V output voltage from a 3.3V supply voltage. The proposed multi-branch charge pump can also reach a very low output voltage ripple of only 0.146% at a load resistance of 1MΩ, which is attributed to the fact that the 8-branch charge pump can transfer charges to the output node eight times consecutively during one clock period. In addition, a high voltage gain of 4.6 is achieved in the 4-stage charge pump at light load conditions. The total chip area is 0.57mm2 in a 0.35µm HV CMOS technology.

As is well known in the design of transformer isolated converters, the transformer leakage inductance causes a large voltage overshoot on the secondary side switching nodes at every switch transition, unless measures are taken to limit the peak voltage stress. Since the peak voltage stress in smart-power integrated converters, where the power devices are integrated on the same die as the controlling logic and supporting circuits, is the major determining factor for the required silicon area for the implementation, this is a major roadblock for the affordable integration of this type of converter. Therefore, any cost-effective smart-power synchronous rectifier requires a voltage clamping circuit that minimizes the voltage stress, while still maintaining the potential advantages of smart-power converters, i.e. minimizing the number and size of the discrete components in the converter. We present an integrated asynchronous active clamping circuit, that can clamp the overshoot voltage to arbitrary voltages while optimizing the efficiency by only being active when required. Because of the asynchronous operation, the size of the required external components is minimized. Measurements on the smart-power IC implementation of the asynchronous active clamp circuit combined with a secondary side synchronous rectifier for a 1 MHz full bridge converter confirm the reduction in voltage stress and the optimization of the efficiency.