In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 µm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

A VCO for multi-standard transceiver should operate in wide-tuning range, while providing low-phase noise quadrature outputs with low power consumption. In this paper, a multi-standard CMOS LC QVCO is designed utilizing reconfigurable LC tank and low power low phase noise quadrature generation method. Designed in 0.18 µm CMOS technology, the VCO achieved very wide tuning characteristics in two separate bands with low power consumption.

As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.

A reconfigurable CMOS mixer for multi-standard application is presented. The mixer can be tuned and adjusted to multi-frequency bands using a flexible matching network which is a kind of variable reactance transformer. The flexible matching network consists of a few switched inductors and capacitors. The mixer has acceptable conversion gain, IIP3 and NF. It operates with a return loss of less than -10 dB through 2-6 GHz except for a few narrow frequency bands.

A simple low power low phase noise LC QVCO (Quadrature Voltage Controlled Oscillator) topology is proposed. The topology minimizes phase noise by eliminating the contributions from the tail current source and coupling transistors. With no more than 3.36 mW power consumption from a 1.2 V power supply, the VCO achieves -124 dBc/Hz phase noise performance at 1 MHz offset from the 2.85 GHz carrier frequency.