Side-channel analysis is one of the most investigated hardware Trojan detection approaches. However, nearly all the side-channel analysis approaches require golden chips for reference, which are hard to obtain actually. Besides, majority of existing Trojan detection algorithms focus on the data similarity and ignore the Trojan misclassification during the detection. In this paper, we propose a cost-sensitive golden chip-free hardware Trojan detection framework, which aims to minimize the probability of Trojan misclassification during the detection. The post-layout simulation data of voltage variations at different process corners is utilized as a golden reference. Further, a classification algorithm based on the combination of principal component analysis and Naïve bayes is exploited to identify the existence of hardware Trojan with a minimum misclassification risk. Experimental results on ASIC demonstrate that the proposed approach improves the detection accuracy ratio compared with the three detection algorithms and distinguishes the Trojan with only 0.27% area occupies even under ±15% process variations.

Reconfigurable computing system is a class of parallel architecture with the ability of computing in hardware to increase performance, while remaining much of flexibility of a software solution. This architecture is particularly suitable for running regular and compute-intensive tasks, nevertheless, most compute-intensive tasks spend most of their running time in nested loops. Polyhedron model is a powerful tool to give a reasonable transformation on such nested loops. In this paper, a number of issues are addressed towards the goal of optimization of affine loop nests for reconfigurable cell array (RCA), such as approach to make the most use of processing elements (PE) while minimizing the communication volume by loop transformation in polyhedron model, determination of tilling form by the intra-statement dependence analysis and determination of tilling size by the tilling form and the RCA size. Experimental results on a number of kernels demonstrate the effectiveness of the mapping optimization approaches developed. Compared with DFG-based optimization approach, the execution performances of 1-d jacobi and matrix multiplication are improved by 28% and 48.47%. Lastly, the run-time complexity is acceptable for the practical cases.

For advanced data-oriented applications in distributed environments, effective information is frequently obtained by integrating or merging various autonomous information sources. There are many problems: how to search information sources, how to resolve their heterogeneity, how to merge or integrate target sources, how to represent information sources with a common protocol, and how to process queries. We have proposed a new language, QUIK, as an extension of a deductive object-oriented database (DOOD) language, QUIXOTE, and extend typical mediator systems. In this paper, we discuss various features of QUIK: programming capabilities as integrating an exchange model and mediator specifications, merging subsumption relations for maintaining consistency, searching alternative information sources by hypothesis generation, and identifying objects.

The existing research on Amdahl's law is limited to multi/many-core processors, and cannot be applied to the important parallel processing architecture of coarse-grained reconfigurable arrays. This paper studies the relation between the multi-level parallelism of block cipher algorithms and the architectural characteristics of coarse-grain reconfigurable arrays. We introduce the key variables that affect the performance of reconfigurable arrays, such as communication overhead and configuration overhead, into Amdahl's law. On this basis, we propose a performance model for coarse-grain reconfigurable block cipher array (CGRBA) based on the extended Amdahl's law. In addition, this paper establishes the optimal integer nonlinear programming model, which can provide a parameter reference for the architecture design of CGRBA. The experimental results show that: (1) reducing the communication workload ratio and increasing the number of configuration pages reasonably can significantly improve the algorithm performance on CGRBA; (2) the communication workload ratio has a linear effect on the execution time.

Focused on network reconnaissance, eavesdropping, and DoS attacks caused by static routing policies, this paper designs a random routing mutation architecture based on the OpenFlow protocol, which takes advantages of the global network view and centralized control in a software-defined network. An entropy matrix of network traffic characteristics is constructed by using volume measurements and characteristic measurements of network traffic. Random routing mutation is triggered according to the result of network anomaly detection, which using a wavelet transform and principal component analysis to handle the above entropy matrix for both spatial and temporal correlations. The generation of a random routing path is specified as a 0-1 knapsack problem, which is calculated using an improved ant colony algorithm. Theoretical analysis and simulation results show that the proposed method not only increases the difficulty of network reconnaissance and eavesdropping but also reduces the impact of DoS attacks on the normal communication in an SDN network.

The interrupting characteristics of low voltage current limiting circuit breakers have directly relationship with the magnitude and distribution of magnetic field produced by contact system and splitter plates. In order to analyze the influence of configuration of contact system on current limiting characteristics, 3D magnetic field of arc chamber (including contact system, arc, splitter plates) is calculated. Furthermore, the electromagnetic repulsion force of movable contact is also calculated. The results can be used to improve configuration of arc quenching chamber. The cooperation between operating mechanism and electromagnetic repulsion force is also analyzed in this paper.

With the advancement of technologies in wireless communication and computer down-sizing, it becomes possible to access a global network using handy terminals which are equipped with wireless communication facilities. In such a mobile computing environment, data management is one of the primary objectives of effective computer uses. However, since conventional distributed data management technologies assume that servers and clients are fixed at certain locations in a network, they do not provide any tools to construct advanced applications which make full use of dynamically changing information in such an environment. In this paper, in order to incorporate data distributed over mobile computing environment, we propose a dynamic data integration mechanism called MobiView which is an enhanced view mechanism of a conventional database system. In MobiView, we introduce four methods for database indication without using conventional host name or its local name: host-specified, cell-specified, location-dependent, and MobiView-oriented, through which we discuss how to handle both mobile database servers and mobile database clients.

A coarse-grained reconfigurable architecture (CGRA) is typically hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many computation-intensive kernels (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. Thus, mapping optimization of loop nests is very important to improve the performance of CGRA. Processing element (PE) utilization rate, communication volume and reconfiguration cost are three crucial factors for the performance of RPUs. Loop transformations can affect these three performance influencing factors greatly, and would be of much significance when mapping loops onto RPUs. In this paper, a joint loop transformation approach for RPUs is proposed, where the PE utilization rate, communication cost and reconfiguration cost are under a joint consideration. Our approach could be integrated into compilers for CGRAs to improve the operating performance. Compared with the communication-minimal approach, experimental results show that our scheme can improve 5.8% and 13.6% of execution time on motion estimation (ME) and partial differential equation (PDE) solvers kernels, respectively. Also, run-time complexity is acceptable for the practical cases.

Satellite clusters have been satisfactorily implemented in a number of applications, such as positioning and sensor networks, with the purpose of improving communication system capabilities. However, because the use of clusters requires good management of the resources, those solutions imply new challenges for communication systems. This paper focuses on improving the data management between network elements by considering a network formed by satellite clusters. Satellite clusters work in cooperation to provide real-time and non-real-time services in different footprint areas. This study proposes the adjustable energy consumption access scheme (AECS) as one possible solution response to particular necessities of communication and at the same time, as a way of decreasing the system energy consumption. Energy consumption is a key issue that concerns green network operations and it is directly linked to the cooperation and coordination between network elements. On the other hand, we support the implementation of Optical Inter-Satellite Links (OISL) for communication between cluster elements. The analysis involves the study of energy consumption, transmission delay, specific link margins, bit error rate (BER) and QoS.

The coarse-grained reconfigurable architecture (CGRA) is a promising computing platform that provides both high performance and high power-efficiency. The computation-intensive portions of an application (e.g. loop nests) are often mapped onto CGRA for acceleration. However, mapping loop nests onto CGRA efficiently is quite a challenge due to the special characteristics of CGRA. To optimize the mapping of loop nests onto CGRA, this paper makes three contributions: i) Establishing a precise performance model of mapping loop nests onto CGRA, ii) Formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, iii) Extracting an efficient heuristic algorithm and building a complete flow of mapping loop nests onto CGRA (PolyMAP). Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 27% on average, as compared to the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

A new identification algorithm based on output over-sampling scheme is proposed for a IIR model whose input signal can not be available directly. By using only an output signal sampled at higher rate than unknown input, parameters of the IIR model can be identified. It is clarified that the consistency of the obtained parameter estimates is assured under some specified conditions. Further an efficient recursive algorithm for blind parameter estimation is also given for practical applications. Simulation results demonstrate its effectiveness in both system and channel identification.

Metric learning aims to generate similarity-preserved low dimensional feature vectors from input images. Most existing supervised deep metric learning methods usually define a carefully-designed loss function to make a constraint on relative position between samples in projected lower dimensional space. In this paper, we propose a novel architecture called Naive Similarity Discriminator (NSD) to learn the distribution of easy samples and predict their probability of being similar. Our purpose lies on encouraging generator network to generate vectors in fitting positions whose similarity can be distinguished by our discriminator. Adequate comparison experiments was performed to demonstrate the ability of our proposed model on retrieval and clustering tasks, with precision within specific radius, normalized mutual information and F1 score as evaluation metrics.

Many nodes in Internet of Things (IoT) rely on batteries for power. Additionally, the demand for executing compute-intensive and latency-sensitive tasks is increasing for IoT nodes. In some practical scenarios, the computation tasks of WDs have the non-separable characteristic, that is, binary offloading strategies should be used. In this paper, we focus on the design of an efficient binary offloading algorithm that minimizes system energy consumption (EC) for TDMA-based wireless-powered multi-access edge computing networks, where WDs either compute tasks locally or offload them to hybrid access points (H-APs). We formulate the EC minimization problem which is a non-convex problem and decompose it into a master problem optimizing binary offloading decision and a subproblem optimizing WPT duration and task offloading transmission durations. For the master problem, a DRL based method is applied to obtain the near-optimal offloading decision. For the subproblem, we firstly consider the scenario where the nodes do not have completion time constraints and obtain the optimal analytical solution. Then we consider the scenario with the constraints. By jointly using the Golden Section Method and bisection method, the optimal solution can be obtained due to the convexity of the constraint function. Simulation results show that the proposed offloading algorithm based on DRL can achieve the near-minimal EC.