A 1.8 V, 5 GHz low power frequency synthesizer for Wireless Sensor Networks is presented in 0.18 µm CMOS technology. A low power phase-switching prescaler is designed, and the current mode phase rotator is merged into the first divide-by-2 circuit of the prescaler to reduce power and propagation delay. An improved charge pump circuit is proposed to compensate for the dynamic effects with the charge pump. By a divide-by-2 circuit, the frequency synthesizer can provide a 2.324-2.714 GHz quadrature output frequency in 1 MHz steps with a 4 MHz reference frequency. The measured output phase noise is -110 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL is 11.2 mW at 1.8 V supply voltage.

In this paper we establish a secure communication model where eavesdropper and intended receiver have multiple antennas. We use cooperation and jamming to achieve physical layer security. First, we study how to allocate power between the information bearing signal and the jamming signal. Second, based on this model, we also jointly optimize both the information bearing signal weights and the jamming signal weights to improve physical layer security. The optimal power allocation and the weights are obtained via an iteration algorithm to maximize the secrecy rate. Comparing with equal power allocation and some other different methods, it shows that using cooperative relaying and jamming can significantly improve the physical layer security from the simulation results.

In this paper, a modified Belief Propagation (BP) decoding algorithm for low-density parity check (LDPC) codes based on minimum mean square error (MMSE) criterion is proposed. This modified algorithm uses linear equation to replace the hyperbolic function in the original BP algorithm and optimizes the linear approximation error based on MMSE criterion. As a result, compared with the standard BP algorithm the computational complexity is reduced significantly as the modified algorithm requires only addition operations to implement. Besides that simulation results show our modified algorithm can achieve an error performance very close to the BP algorithm on the additive white Gaussian noise channel.

We consider wireless secure communications between a source and a destination aided by a multi-antenna relay, in the presence of an eavesdropper. In particular, two cooperation schemes of the relay are explored: cooperative relaying (CR) and cooperative jamming (CJ). We first investigate the transmit weight optimization of CR and CJ, for both cases with and without the eavesdropper's channel state information (ECSI). Then, for the case with ECSI, we derive the conditions under which CR achieves a higher secrecy rate than CJ; for the case without ECSI, we compare the secrecy rates of CR and CJ in high transmit power regimes. Building on this, we propose a novel hybrid scheme in which the relay utilizes both CR and CJ, and study the power allocation of the relay between CR and CJ for maximizing the secrecy rate under individual power constraints. Further, we study the case with imperfect channel state information (CSI) for both CR and CJ. At last, extensive numerical results are provided.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35 µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500 kHz to 280 MHz, with a correction error within 50%1% under 200 MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.

In this letter a new analytical method is presented for estimating the timing jitter of CMOS ring oscillators due to power supply noise. Predictive jitter equation is presented, and the proposed method is utilized to study the jitter induced by power supply noise in an inverter-based ring oscillator, which is designed and simulated in SMIC 0.13-µm standard CMOS process. A comparison between the results obtained by the proposed method and those obtained by HSPICE simulation proves the accuracy of the predictive equation. Most of the errors between the theoretic calculation and simulation results are less than 3 ps.

We consider secure wireless communications, where a source is communicating to a destination in the presence of K (K > 1) eavesdroppers. The source and destination both are equipped with multiple antennas, while each eavesdropper has a single antenna. The source aims to maximize the communication rate to the destination, while concealing the message from all the eavesdroppers. Combined with selective diversity, we propose a heuristic secrecy transmission scheme where the multiple-input-multiple-output (MIMO) secrecy channel is simplified into a multiple-input-single-output (MISO) one with the highest orthogonality to the eavesdropper channels. Then convex optimization is applied to obtain the optimal transmit covariance matrix for this selected MISO secrecy channel. Numerical results are provided to illustrate the efficacy of the proposed scheme.