The search functionality is under construction.
The search functionality is under construction.

Author Search Result

[Author] Jing YE(2hit)

1-2hit
  • A Fast Algorithm for Liquid Voting on Blockchain

    Xiaoping ZHOU  Peng LI  Yulong ZENG  Xuepeng FAN  Peng LIU  Toshiaki MIYAZAKI  

     
    PAPER

      Pubricized:
    2021/05/17
      Vol:
    E104-D No:8
      Page(s):
    1163-1171

    Blockchain-based voting, including liquid voting, has been extensively studied in recent years. However, it remains challenging to implement liquid voting on blockchain using Ethereum smart contract. The challenge comes from the gas limit, which is that the number of instructions for processing a ballot cannot exceed a certain amount. This restricts the application scenario with respect to algorithms whose time complexity is linear to the number of voters, i.e., O(n). As the blockchain technology can well share and reuse the resources, we study a model of liquid voting on blockchain and propose a fast algorithm, named Flash, to eliminate the restriction. The key idea behind our algorithm is to shift some on-chain process to off-chain. In detail, we first construct a Merkle tree off-chain which contains all voters' properties. Second, we use Merkle proof and interval tree to process each ballot with O(log n) on-chain time complexity. Theoretically, the algorithm can support up to 21000 voters with respect to the current gas limit on Ethereum. Experimentally, the result implies that the consumed gas fee remains at a very low level when the number of voters increases. This means our algorithm makes liquid voting on blockchain practical even for massive voters.

  • LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

    Yu HU  Jing YE  Zhiping SHI  Xiaowei LI  

     
    PAPER-Dependable Computing

      Pubricized:
    2016/10/25
      Vol:
    E100-D No:2
      Page(s):
    323-331

    Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.