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[Author] Junko NAKAJIMA(4hit)

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  • Performance Analysis and Parallel Implementation of Dedicated Hash Functions on Pentium III

    Junko NAKAJIMA  Mitsuru MATSUI  

     
    PAPER-Symmetric Ciphers and Hash Functions

      Vol:
    E86-A No:1
      Page(s):
    54-63

    This paper shows an extensive software performance analysis of dedicated hash functions, particularly concentrating on Pentium III, which is a current dominant processor. The targeted hash functions are MD5, RIPEMD-128 -160, SHA-1 -256 -512 and Whirlpool, which fully cover currently used and future promised hashing algorithms. We try to optimize hashing speed not only by carefully arranging pipeline scheduling but also by processing two or even three message blocks in parallel using MMX registers for 32-bit oriented hash functions. Moreover we thoroughly utilize 64-bit MMX instructions for maximizing performance of 64-bit oriented hash functions, SHA-512 and Whirlpool. To our best knowledge, this paper gives the first detailed measured performance analysis of SHA-256, SHA-512 and Whirlpool.

  • Fast Software Implementations of MISTY1 on Alpha Processors

    Junko NAKAJIMA  Mitsuru MATSUI  

     
    PAPER

      Vol:
    E82-A No:1
      Page(s):
    107-116

    In this paper, we show two methods for fast software implementations of block cipher algorithm MISTY1 on Digital Alpha processors. One is based on the method proposed by Biham at the fourth Fast Software Encryption Workshop. This method, which is called "bitslice," realizes high performance by regarding the target cipher as a collection of logic gates and processing plural blocks in parallel, although its data format is non-standard. The other is standard implementation where all modes of operation are available. We analyze the architecture of Alpha and discuss how to optimize MISTY1 on the processor. As a result, our assembly language programs achieved an encryption speed of 288 Mbps for the bitslice version and 105 Mbps for the standard version, respectively, on Alpha 21164A (500 MHz).

  • A Small and Fast Software Implementation of Elliptic Curve Cryptosystems over GF(p) on a 16-Bit Microcomputer

    Toshio HASEGAWA  Junko NAKAJIMA  Mitsuru MATSUI  

     
    PAPER

      Vol:
    E82-A No:1
      Page(s):
    98-106

    Recently the study and implementation of elliptic curve cryptosystems (ECC) have developed rapidly and its achievements have become a center of attraction. ECC has the advantage of high-speed processing in software even on restricted environments such as smart cards. In this paper, we concentrate on complete software implementation of ECC over a prime field on a 16-bit microcomputer M16C (10 MHz). We propose a new type of prime characteristic of base field suitable for small and fast implementation, and also improve basic elliptic arithmetic formulas. We report a small and fast software implementation of a cryptographic library which supports 160-bit elliptic curve DSA (ECDSA) signature generation, verification and SHA-1 on the processor. This library also includes general integer arithmetic routines for applicability to other cryptographic algorithms. We successfully implemented the library in 4 Kbyte code/data size including SHA-1, and confirmed a speed of 150 msec for generating an ECDSA signature and 630 msec for verifying an ECDSA signature on M16C.

  • The 128-Bit Block Cipher Camellia

    Kazumaro AOKI  Tetsuya ICHIKAWA  Masayuki KANDA  Mitsuru MATSUI  Shiho MORIAI  Junko NAKAJIMA  Toshio TOKITA  

     
    PAPER

      Vol:
    E85-A No:1
      Page(s):
    11-24

    We present the new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway. It was also designed to suit both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (1.13 GHz) at the rate of 471 Mbits per second. In addition, a distinguishing feature is its small hardware design. A hardware implementation, which includes encryption, decryption, and the key schedule for 128-bit keys, occupies only 9.66 K gates using a 0.35 µm CMOS ASIC library. This is in the smallest class among all existing 128-bit block ciphers. It perfectly meets the current market requirements in wireless cards, for instance, where low power consumption is essential.