This paper presents a pulsed sensing scheme with a limited bit-line swing designed for 4-Mb CMOS high-speed DRAM's (HSDRAM's) and beyond. It uses a standard CMOS cross-coupled sense amplifier and limits the swing by means of a pulsed sense clock. The signal loss that would occur if the bit-line swing was not exactly limited to one threshold above the word-line's low level is avoided by using a small reference voltage generator and trench decoupling capacitors. The new sensing scheme was successfully implemented on an experimental HSDRAM fabricated by using 0.7-µm Leff CMOS technology, and thus a high-speed random access time of 15 ns and a low power dissipation of 144 mW were obtained for 512-kb array activation with a fast cycle time of 60 ns at 3.6 V.